diff --git a/artiq/coredevice/comm_dummy.py b/artiq/coredevice/comm_dummy.py index 842e00f9c..b9eb648fe 100644 --- a/artiq/coredevice/comm_dummy.py +++ b/artiq/coredevice/comm_dummy.py @@ -15,9 +15,6 @@ class _RuntimeEnvironment(LinkInterface): class Comm(AutoDB): - class DBKeys: - implicit_core = False - def get_runtime_env(self): return _RuntimeEnvironment(1*ns) diff --git a/artiq/coredevice/comm_serial.py b/artiq/coredevice/comm_serial.py index 63336a537..46e59d14f 100644 --- a/artiq/coredevice/comm_serial.py +++ b/artiq/coredevice/comm_serial.py @@ -64,7 +64,6 @@ class Comm(AutoDB): class DBKeys: serial_dev = Parameter("/dev/ttyUSB1") baud_rate = Parameter(115200) - implicit_core = False def build(self): self.port = serial.serial_for_url(self.serial_dev, baudrate=115200) diff --git a/artiq/coredevice/core.py b/artiq/coredevice/core.py index d592e5033..41181349e 100644 --- a/artiq/coredevice/core.py +++ b/artiq/coredevice/core.py @@ -48,7 +48,6 @@ class Core(AutoDB): class DBKeys: comm = Device() external_clock = Parameter(None) - implicit_core = False def build(self): self.runtime_env = self.comm.get_runtime_env() diff --git a/artiq/coredevice/dds.py b/artiq/coredevice/dds.py index 2fba939e8..c0ab079e7 100644 --- a/artiq/coredevice/dds.py +++ b/artiq/coredevice/dds.py @@ -25,6 +25,7 @@ class DDS(AutoDB): """ class DBKeys: + core = Device() dds_sysclk = Parameter(1*GHz) reg_channel = Argument() rtio_switch = Argument() diff --git a/artiq/coredevice/gpio.py b/artiq/coredevice/gpio.py index 982ec1fc7..9477da861 100644 --- a/artiq/coredevice/gpio.py +++ b/artiq/coredevice/gpio.py @@ -4,6 +4,7 @@ from artiq.language.db import * class GPIOOut(AutoDB): class DBKeys: + core = Device() channel = Argument() @kernel diff --git a/artiq/coredevice/rtio.py b/artiq/coredevice/rtio.py index bb548aad4..e28f06e06 100644 --- a/artiq/coredevice/rtio.py +++ b/artiq/coredevice/rtio.py @@ -13,6 +13,7 @@ class LLRTIOOut(AutoDB): """ class DBKeys: + core = Device() channel = Argument() def build(self): @@ -53,6 +54,7 @@ class LLRTIOOut(AutoDB): class _RTIOBase(AutoDB): class DBKeys: + core = Device() channel = Argument() def build(self): diff --git a/artiq/devices/pdq2/mediator.py b/artiq/devices/pdq2/mediator.py index 5ad2180c0..bc811247d 100644 --- a/artiq/devices/pdq2/mediator.py +++ b/artiq/devices/pdq2/mediator.py @@ -113,6 +113,7 @@ class _Frame: class CompoundPDQ2(AutoDB): class DBKeys: + core = Device() ids = Argument() rtio_trigger = Argument() rtio_frame = Argument() diff --git a/artiq/frontend/artiq_run.py b/artiq/frontend/artiq_run.py index 8242422db..2fe01b5e7 100755 --- a/artiq/frontend/artiq_run.py +++ b/artiq/frontend/artiq_run.py @@ -19,7 +19,6 @@ from artiq.tools import file_import, verbosity_args, init_logger class ELFRunner(AutoDB): class DBKeys: comm = Device() - implicit_core = False def run(self, filename): with open(filename, "rb") as f: diff --git a/artiq/language/db.py b/artiq/language/db.py index 21be55a2a..be45baed2 100644 --- a/artiq/language/db.py +++ b/artiq/language/db.py @@ -75,20 +75,12 @@ class AutoDB: def __init__(self, dbh=None, **kwargs): self.dbh = dbh - dbkeys = self.DBKeys() - if getattr(dbkeys, "implicit_core", True): - if hasattr(dbkeys, "core"): - raise ValueError( - "Set implicit_core to False when" - " core is explicitly specified") - dbkeys.core = Device() - for k, v in kwargs.items(): object.__setattr__(self, k, v) - for k in dir(dbkeys): + for k in dir(self.DBKeys): if k not in self.__dict__: - ak = getattr(dbkeys, k) + ak = getattr(self.DBKeys, k) if isinstance(ak, Argument): if ak.default is NoDefault: raise AttributeError( diff --git a/artiq/sim/devices.py b/artiq/sim/devices.py index 7dc4ef4c0..c5900a405 100644 --- a/artiq/sim/devices.py +++ b/artiq/sim/devices.py @@ -1,15 +1,12 @@ from random import Random from artiq.language.core import delay, kernel -from artiq.language.db import AutoDB, Argument +from artiq.language.db import * from artiq.language import units from artiq.sim import time class Core(AutoDB): - class DBKeys: - implicit_core = False - _level = 0 def run(self, k_function, k_args, k_kwargs): @@ -23,6 +20,7 @@ class Core(AutoDB): class Input(AutoDB): class DBKeys: + core = Device() name = Argument() def build(self): @@ -44,6 +42,7 @@ class Input(AutoDB): class WaveOutput(AutoDB): class DBKeys: + core = Device() name = Argument() @kernel @@ -54,6 +53,7 @@ class WaveOutput(AutoDB): class VoltageOutput(AutoDB): class DBKeys: + core = Device() name = Argument() @kernel diff --git a/artiq/test/full_stack.py b/artiq/test/full_stack.py index e1a5edc28..9d37e160f 100644 --- a/artiq/test/full_stack.py +++ b/artiq/test/full_stack.py @@ -30,6 +30,7 @@ def _run_on_host(k_class, **parameters): class _Primes(AutoDB): class DBKeys: + core = Device() output_list = Argument() maximum = Argument() @@ -85,6 +86,7 @@ class _Misc(AutoDB): class _PulseLogger(AutoDB): class DBKeys: + core = Device() output_list = Argument() name = Argument() @@ -108,6 +110,7 @@ class _PulseLogger(AutoDB): class _Pulses(AutoDB): class DBKeys: + core = Device() output_list = Argument() def build(self): @@ -135,6 +138,7 @@ class _MyException(Exception): class _Exceptions(AutoDB): class DBKeys: + core = Device() trace = Argument() @kernel @@ -258,6 +262,7 @@ class ExecutionCase(unittest.TestCase): class _RTIOLoopback(AutoDB): class DBKeys: + core = Device() i = Device() o = Device() npulses = Argument() @@ -278,6 +283,7 @@ class _RTIOLoopback(AutoDB): class _RTIOUnderflow(AutoDB): class DBKeys: + core = Device() o = Device() @kernel @@ -289,6 +295,7 @@ class _RTIOUnderflow(AutoDB): class _RTIOSequenceError(AutoDB): class DBKeys: + core = Device() o = Device() @kernel diff --git a/benchmarks/pulse_rate.py b/benchmarks/pulse_rate.py index 3c2747d98..da0d3f34c 100644 --- a/benchmarks/pulse_rate.py +++ b/benchmarks/pulse_rate.py @@ -6,6 +6,7 @@ class PulseRate(AutoDB): __artiq_unit__ = "Pulse rate" class DBKeys: + core = Device() ttl0 = Device() pulse_rate = Result() diff --git a/benchmarks/rpc_timing.py b/benchmarks/rpc_timing.py index 692186c16..483085534 100644 --- a/benchmarks/rpc_timing.py +++ b/benchmarks/rpc_timing.py @@ -7,6 +7,7 @@ class RPCTiming(AutoDB): __artiq_unit__ = "RPC timing" class DBKeys: + core = Device() repeats = Argument(100) rpc_time_mean = Result() rpc_time_stddev = Result() diff --git a/benchmarks/rtio_skew.py b/benchmarks/rtio_skew.py index be914c9cd..fc86c4d24 100644 --- a/benchmarks/rtio_skew.py +++ b/benchmarks/rtio_skew.py @@ -9,6 +9,7 @@ class RTIOSkew(AutoDB): __artiq_unit__ = "RTIO skew" class DBKeys: + core = Device() pmt0 = Device() ttl0 = Device() rtio_skew = Result() diff --git a/doc/manual/getting_started.rst b/doc/manual/getting_started.rst index ff576918e..93c907011 100644 --- a/doc/manual/getting_started.rst +++ b/doc/manual/getting_started.rst @@ -13,6 +13,7 @@ As a very first step, we will turn on a LED on the core device. Create a file `` __artiq_unit__ = "ARTIQ tutorial" class DBKeys: + core = Device() led = Device() @kernel @@ -46,6 +47,7 @@ Modify the code as follows: :: __artiq_unit__ = "ARTIQ tutorial" class DBKeys: + core = Device() led = Device() @kernel @@ -91,6 +93,7 @@ Create a new file ``rtio.py`` containing the following: :: __artiq_unit__ = "ARTIQ tutorial" class DBKeys: + core = Device() ttl0 = Device() @kernel @@ -115,6 +118,7 @@ Try reducing the period of the generated waveform until the CPU cannot keep up w __artiq_unit__ = "ARTIQ tutorial" class DBKeys: + core = Device() led = Device() ttl0 = Device() diff --git a/examples/master/repository/dds_test.py b/examples/master/repository/dds_test.py index 86fc0efb8..de342e5ea 100644 --- a/examples/master/repository/dds_test.py +++ b/examples/master/repository/dds_test.py @@ -5,6 +5,7 @@ class DDSTest(AutoDB): __artiq_unit__ = "DDS test" class DBKeys: + core = Device() dds0 = Device() dds1 = Device() dds2 = Device() diff --git a/examples/master/repository/flopping_f_simulation.py b/examples/master/repository/flopping_f_simulation.py index c63fe1dd6..b16518799 100644 --- a/examples/master/repository/flopping_f_simulation.py +++ b/examples/master/repository/flopping_f_simulation.py @@ -28,8 +28,6 @@ class FloppingF(AutoDB): __artiq_gui_file__ = "flopping_f_simulation_gui.py" class DBKeys: - implicit_core = False - npoints = Argument(100) min_freq = Argument(1000) max_freq = Argument(2000) diff --git a/examples/master/repository/mandelbrot.py b/examples/master/repository/mandelbrot.py index 1249ea2a8..d3eae965e 100644 --- a/examples/master/repository/mandelbrot.py +++ b/examples/master/repository/mandelbrot.py @@ -6,6 +6,9 @@ from artiq import * class Mandelbrot(AutoDB): __artiq_unit__ = "Mandelbrot set demo" + class DBKeys: + core = Device() + def col(self, i): sys.stdout.write(" .,-:;i+hHM$*#@ "[i]) diff --git a/examples/master/repository/photon_histogram.py b/examples/master/repository/photon_histogram.py index 20d11704a..1e8379243 100644 --- a/examples/master/repository/photon_histogram.py +++ b/examples/master/repository/photon_histogram.py @@ -5,6 +5,7 @@ class PhotonHistogram(AutoDB): __artiq_unit__ = "Photon histogram" class DBKeys: + core = Device() bd = Device() bdd = Device() pmt = Device() diff --git a/examples/master/repository/transport.py b/examples/master/repository/transport.py index 2d0a42db4..528da06cb 100644 --- a/examples/master/repository/transport.py +++ b/examples/master/repository/transport.py @@ -14,6 +14,7 @@ class Transport(AutoDB): __artiq_unit__ = "Transport" class DBKeys: + core = Device() bd = Device() bdd = Device() pmt = Device() diff --git a/examples/sim/al_spectroscopy.py b/examples/sim/al_spectroscopy.py index c40850d09..01de7ee1b 100644 --- a/examples/sim/al_spectroscopy.py +++ b/examples/sim/al_spectroscopy.py @@ -5,6 +5,7 @@ class AluminumSpectroscopy(AutoDB): __artiq_unit__ = "Aluminum spectroscopy (simulation)" class DBKeys: + core = Device() mains_sync = Device() laser_cooling = Device() spectroscopy = Device() diff --git a/examples/sim/simple_simulation.py b/examples/sim/simple_simulation.py index 3efbed89a..798d9a149 100644 --- a/examples/sim/simple_simulation.py +++ b/examples/sim/simple_simulation.py @@ -5,6 +5,7 @@ class SimpleSimulation(AutoDB): __artiq_unit__ = "Simple simulation" class DBKeys: + core = Device() a = Device() b = Device() c = Device()