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phaser: fix widths

This commit is contained in:
Robert Jördens 2016-11-18 17:24:11 +01:00
parent bcde26f990
commit 0ee47e77ae
1 changed files with 3 additions and 2 deletions
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5
artiq/gateware/dsp/sawg.py
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@ -58,7 +58,7 @@ class SplineParallelDUC(ParallelDDS):
self.submodules += p, f self.submodules += p, f
self.ce = Signal(reset=1) self.ce = Signal(reset=1)
self.clr = Signal() self.clr = Signal()
super().__init__(widths._replace(p=len(self.f.a0), f=len(self.f.a0)), super().__init__(widths._replace(p=len(self.p.a0), f=len(self.f.a0)),
**kwargs) **kwargs)
self.latency += f.latency self.latency += f.latency
@ -146,7 +146,8 @@ class Channel(Module, SatAddMixin):
self.submodules.a1 = a1 = SplineParallelDDS(widths, orders) self.submodules.a1 = a1 = SplineParallelDDS(widths, orders)
self.submodules.a2 = a2 = SplineParallelDDS(widths, orders) self.submodules.a2 = a2 = SplineParallelDDS(widths, orders)
self.submodules.b = b = SplineParallelDUC( self.submodules.b = b = SplineParallelDUC(
widths, orders, parallelism=parallelism, a_delay=-a1.latency) widths._replace(a=len(a1.xo[0])), orders,
parallelism=parallelism, a_delay=-a1.latency)
cfg = Config(widths.a) cfg = Config(widths.a)
u = Spline(width=widths.a, order=orders.a) u = Spline(width=widths.a, order=orders.a)
du = Delay(widths.a, a1.latency + b.latency - u.latency) du = Delay(widths.a, a1.latency + b.latency - u.latency)