From 0e640a6d6ff2dc84754cd7b724e8d140170c9f7f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 18 Jun 2018 17:04:12 +0800 Subject: [PATCH] hmc7043: fix SYSREF to meet s/h at FPGA (#794) --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index 4879427fa..f9018084e 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -172,7 +172,7 @@ pub mod hmc7043 { (false, 0, 0x0, 0x0, 0x08), // 4: ADC2_CLK (false, 0, 0x0, 0x0, 0x08), // 5: ADC2_SYSREF (false, 0, 0x0, 0x0, 0x08), // 6: GTP_CLK2 - (true, SYSREF_DIV, 0x0, 0x0, 0x10), // 7: FPGA_DAC_SYSREF, LVDS + (true, SYSREF_DIV, 0x0, 0x2, 0x10), // 7: FPGA_DAC_SYSREF, LVDS (true, FPGA_CLK_DIV, 0x0, 0x0, 0x08), // 8: GTP_CLK1 (false, 0, 0x0, 0x0, 0x10), // 9: AMC_MASTER_AUX_CLK (false, 0, 0x0, 0x0, 0x10), // 10: RTM_MASTER_AUX_CLK