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rtio/sed: quash writes to LogChannel

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This commit is contained in:
Sebastien Bourdeauducq 2017-09-16 15:19:30 +08:00
parent 1cfe90b1d9
commit 0e25154e25
3 changed files with 19 additions and 8 deletions
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4
artiq/gateware/rtio/core.py
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@ -222,7 +222,9 @@ class Core(Module, AutoCSR):
self.submodules += inputs
# Outputs
outputs = SED(channels, "async", interface=self.cri)
outputs = SED(channels, "async",
quash_channels=[n for n, c in enumerate(channels) if isinstance(c, LogChannel)],
interface=self.cri)
self.submodules += outputs
self.comb += outputs.coarse_timestamp.eq(coarse_ts)
self.sync += outputs.minimum_coarse_timestamp.eq(coarse_ts + 16)

4
artiq/gateware/rtio/sed/core.py
View File

@ -12,7 +12,8 @@ __all__ = ["SED"]
class SED(Module):
def __init__(self, channels, mode, enable_spread=True, lane_count=8, fifo_depth=128, interface=None):
def __init__(self, channels, mode, lane_count=8, fifo_depth=128, enable_spread=True,
quash_channels=[], interface=None):
if mode == "sync":
lane_dist_cdr = lambda x: x
fifos_cdr = lambda x: x
@ -34,6 +35,7 @@ class SED(Module):
LaneDistributor(lane_count, seqn_width,
layouts.fifo_payload(channels), fine_ts_width,
enable_spread=enable_spread,
quash_channels=quash_channels,
interface=interface))
self.submodules.fifos = fifos_cdr(
FIFOs(lane_count, fifo_depth,

19
artiq/gateware/rtio/sed/lane_distributor.py
View File

@ -8,13 +8,13 @@ __all__ = ["LaneDistributor"]
# CRI write happens in 3 cycles:
# 1. set timestamp
# 1. set timestamp and channel
# 2. set other payload elements and issue write command
# 3. check status
class LaneDistributor(Module):
def __init__(self, lane_count, seqn_width, layout_payload, fine_ts_width,
enable_spread=True, interface=None):
enable_spread=True, quash_channels=[], interface=None):
if lane_count & (lane_count - 1):
raise NotImplementedError("lane count must be a power of 2")
@ -52,7 +52,7 @@ class LaneDistributor(Module):
if hasattr(lio.payload, "data"):
self.comb += lio.payload.data.eq(self.cri.o_data)
# when timestamp arrives in cycle #1, prepare computations
# when timestamp and channel arrive in cycle #1, prepare computations
coarse_timestamp = Signal(64-fine_ts_width)
self.comb += coarse_timestamp.eq(self.cri.timestamp[fine_ts_width:])
timestamp_above_min = Signal()
@ -76,6 +76,11 @@ class LaneDistributor(Module):
)
]
quash = Signal()
self.sync += quash.eq(0)
for channel in quash_channels:
self.sync += If(self.cri.chan_sel[:16] == channel, quash.eq(1))
# cycle #2, write
timestamp_above_lane_min = Signal()
do_write = Signal()
@ -83,9 +88,11 @@ class LaneDistributor(Module):
do_sequence_error = Signal()
self.comb += [
timestamp_above_lane_min.eq(Mux(use_laneB, timestamp_above_laneB_min, timestamp_above_laneA_min)),
do_write.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & timestamp_above_lane_min),
do_underflow.eq((self.cri.cmd == cri.commands["write"]) & ~timestamp_above_min),
do_sequence_error.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & ~timestamp_above_lane_min),
If(~quash,
do_write.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & timestamp_above_lane_min),
do_underflow.eq((self.cri.cmd == cri.commands["write"]) & ~timestamp_above_min),
do_sequence_error.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & ~timestamp_above_lane_min),
),
Array(lio.we for lio in self.output)[use_lanen].eq(do_write)
]
self.sync += [