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targets/kc705/qc2: hook up HPC backplane

This commit is contained in:
Sebastien Bourdeauducq 2016-03-16 16:19:56 +08:00
parent cb8e497ff6
commit 0e1f75ec49
2 changed files with 89 additions and 80 deletions
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106
artiq/gateware/nist_qc2.py
View File

@ -1,66 +1,66 @@
import itertools
from migen.build.generic_platform import * from migen.build.generic_platform import *
fmc_adapter_io = [ __all__ = ["fmc_adapter_io"]
("ttl", 0, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
("ttl", 1, Pins("LPC:LA02_P"), IOStandard("LVTTL")),
("ttl", 2, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
("ttl", 3, Pins("LPC:LA02_N"), IOStandard("LVTTL")),
("ttl", 4, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
("ttl", 5, Pins("LPC:LA01_CC_N"), IOStandard("LVTTL")),
("ttl", 6, Pins("LPC:LA06_P"), IOStandard("LVTTL")),
("ttl", 7, Pins("LPC:LA06_N"), IOStandard("LVTTL")),
("ttl", 8, Pins("LPC:LA05_P"), IOStandard("LVTTL")),
("ttl", 9, Pins("LPC:LA05_N"), IOStandard("LVTTL")),
("ttl", 10, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
("ttl", 11, Pins("LPC:LA09_P"), IOStandard("LVTTL")),
("ttl", 12, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
("ttl", 13, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
("ttl", 14, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
("ttl", 15, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
("ttl", 16, Pins("LPC:LA13_N"), IOStandard("LVTTL")),
("ttl", 17, Pins("LPC:LA14_N"), IOStandard("LVTTL")),
("ttl", 18, Pins("LPC:LA17_CC_P"), IOStandard("LVTTL")),
("ttl", 19, Pins("LPC:LA17_CC_N"), IOStandard("LVTTL")),
("ttl", 20, Pins("LPC:LA18_CC_P"), IOStandard("LVTTL")),
("ttl", 21, Pins("LPC:LA18_CC_N"), IOStandard("LVTTL")),
("ttl", 22, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
("ttl", 23, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
("ttl", 24, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
("ttl", 25, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
("ttl", 26, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
("ttl", 27, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
("dds", 0, ttl_pins = [
Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N " "LA00_CC_P", "LA02_P", "LA00_CC_N", "LA02_N", "LA01_CC_P", "LA01_CC_N", "LA06_P", "LA06_N",
"LPC:LA20_N LPC:LA19_P LPC:LA20_P")), "LA05_P", "LA05_N", "LA10_P", "LA09_P", "LA10_N", "LA09_N", "LA13_P", "LA14_P", "LA13_N",
Subsignal("d", Pins("LPC:LA15_N LPC:LA16_N LPC:LA15_P LPC:LA16_P " "LA14_N", "LA17_CC_P", "LA17_CC_N", "LA18_CC_P", "LA18_CC_N", "LA23_P", "LA23_N", "LA27_P",
"LPC:LA11_N LPC:LA12_N LPC:LA11_P LPC:LA12_P " "LA26_P", "LA27_N", "LA26_N"
"LPC:LA07_N LPC:LA08_N LPC:LA07_P LPC:LA08_P " ]
"LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")),
Subsignal("sel_n", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N " def get_fmc_adapter_io():
"LPC:LA30_N LPC:LA33_P LPC:LA33_N LPC:LA32_P")), ttl = itertools.count()
Subsignal("fud", Pins("LPC:LA21_N")), dds = itertools.count()
Subsignal("wr_n", Pins("LPC:LA24_P")), i2c_fmc = itertools.count()
Subsignal("rd_n", Pins("LPC:LA25_N")), clk_m2c = itertools.count()
Subsignal("rst", Pins("LPC:LA25_P")),
r = []
for connector in "LPC", "HPC":
for ttl_pin in ttl_pins:
r.append(("ttl", next(ttl),
Pins(connector + ":" + ttl_pin), IOStandard("LVTTL")))
def FPins(s):
return Pins(s.replace("FMC:", connector + ":"))
r += [
("dds", next(dds),
Subsignal("a", FPins("FMC:LA22_N FMC:LA21_P FMC:LA22_P FMC:LA19_N "
"FMC:LA20_N FMC:LA19_P FMC:LA20_P")),
Subsignal("d", FPins("FMC:LA15_N FMC:LA16_N FMC:LA15_P FMC:LA16_P "
"FMC:LA11_N FMC:LA12_N FMC:LA11_P FMC:LA12_P "
"FMC:LA07_N FMC:LA08_N FMC:LA07_P FMC:LA08_P "
"FMC:LA04_N FMC:LA03_N FMC:LA04_P FMC:LA03_P")),
Subsignal("sel_n", FPins("FMC:LA24_N FMC:LA29_P FMC:LA28_P FMC:LA29_N "
"FMC:LA28_N FMC:LA31_P FMC:LA30_P FMC:LA31_N "
"FMC:LA30_N FMC:LA33_P FMC:LA33_N FMC:LA32_P")),
Subsignal("fud", FPins("FMC:LA21_N")),
Subsignal("wr_n", FPins("FMC:LA24_P")),
Subsignal("rd_n", FPins("FMC:LA25_N")),
Subsignal("rst", FPins("FMC:LA25_P")),
IOStandard("LVTTL")), IOStandard("LVTTL")),
("i2c_fmc", 0, ("i2c_fmc", next(i2c_fmc),
Subsignal("scl", Pins("LPC:IIC_SCL")), Subsignal("scl", FPins("FMC:IIC_SCL")),
Subsignal("sda", Pins("LPC:IIC_SDA")), Subsignal("sda", FPins("FMC:IIC_SDA")),
IOStandard("LVCMOS25")), IOStandard("LVCMOS25")),
("clk_m2c", 0, ("clk_m2c", next(clk_m2c),
Subsignal("p", Pins("LPC:CLK0_M2C_P")), Subsignal("p", FPins("FMC:CLK0_M2C_P")),
Subsignal("n", Pins("LPC:CLK0_M2C_N")), Subsignal("n", FPins("FMC:CLK0_M2C_N")),
IOStandard("LVDS")), IOStandard("LVDS")),
("clk_m2c", 1, ("clk_m2c", next(clk_m2c),
Subsignal("p", Pins("LPC:CLK1_M2C_P")), Subsignal("p", FPins("FMC:CLK1_M2C_P")),
Subsignal("n", Pins("LPC:CLK1_M2C_N")), Subsignal("n", FPins("FMC:CLK1_M2C_N")),
IOStandard("LVDS")), IOStandard("LVDS")),
] ]
return r
fmc_adapter_io = get_fmc_adapter_io()

27
artiq/gateware/targets/kc705.py
View File

@ -300,7 +300,7 @@ class NIST_CLOCK(_NIST_Ions):
class NIST_QC2(_NIST_Ions): class NIST_QC2(_NIST_Ions):
""" """
NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
and 12 DDS channels. Current implementation for single backplane. and 24 DDS channels.
""" """
def __init__(self, cpu_type="or1k", **kwargs): def __init__(self, cpu_type="or1k", **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs) _NIST_Ions.__init__(self, cpu_type, **kwargs)
@ -309,16 +309,25 @@ class NIST_QC2(_NIST_Ions):
platform.add_extension(nist_qc2.fmc_adapter_io) platform.add_extension(nist_qc2.fmc_adapter_io)
rtio_channels = [] rtio_channels = []
clock_generators = []
for backplane_offset in 0, 28:
# TTL0-23 are In+Out capable # TTL0-23 are In+Out capable
for i in range(24): for i in range(24):
phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i)) phy = ttl_serdes_7series.Inout_8X(
platform.request("ttl", backplane_offset+i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# TTL24-26 are output only # TTL24-26 are output only
for i in range(24, 27): for i in range(24, 27):
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) phy = ttl_serdes_7series.Output_8X(
platform.request("ttl", backplane_offset+i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
# TTL27 is for the clock generator
phy = ttl_simple.ClockGen(
platform.request("ttl", backplane_offset+27))
self.submodules += phy
clock_generators.append(rtio.Channel.from_phy(phy))
phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n")) phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
self.submodules += phy self.submodules += phy
@ -328,17 +337,17 @@ class NIST_QC2(_NIST_Ions):
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
# TTL27 is for the clock generator # add clock generators after RTIO_REGULAR_TTL_COUNT
phy = ttl_simple.ClockGen(platform.request("ttl", 27)) rtio_channels += clock_generators
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 1 self.config["RTIO_DDS_COUNT"] = 2
self.config["DDS_CHANNELS_PER_BUS"] = 12 self.config["DDS_CHANNELS_PER_BUS"] = 12
self.config["DDS_AD9914"] = True self.config["DDS_AD9914"] = True
self.config["DDS_ONEHOT_SEL"] = True self.config["DDS_ONEHOT_SEL"] = True
phy = dds.AD9914(platform.request("dds"), 12, onehot=True) for backplane_offset in range(2):
phy = dds.AD9914(
platform.request("dds", backplane_offset), 12, onehot=True)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512, ofifo_depth=512,