forked from M-Labs/artiq
parent
798a5f70df
commit
0d7688017b
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@ -86,14 +86,11 @@ class Target:
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llmachine = lltarget.create_target_machine(
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features=",".join(["+{}".format(f) for f in self.features]),
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reloc="pic", codemodel="default")
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llmachine.set_verbose(True)
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llmachine.set_asm_verbosity(True)
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return llmachine
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def optimize(self, llmodule):
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llmachine = self.target_machine()
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llpassmgr = llvm.create_module_pass_manager()
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llmachine.target_data.add_pass(llpassmgr)
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llmachine.add_analysis_passes(llpassmgr)
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# Register our alias analysis passes.
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llpassmgr.add_basic_alias_analysis_pass()
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@ -37,9 +37,16 @@ def memoize(generator):
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class DebugInfoEmitter:
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def __init__(self, llmodule):
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self.llmodule = llmodule
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self.llsubprograms = []
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self.llcompileunit = None
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self.cache = {}
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llident = self.llmodule.add_named_metadata('llvm.ident')
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llident.add(self.emit_metadata(["ARTIQ"]))
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llflags = self.llmodule.add_named_metadata('llvm.module.flags')
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llflags.add(self.emit_metadata([2, "Debug Info Version", 3]))
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llflags.add(self.emit_metadata([2, "Dwarf Version", 4]))
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def emit_metadata(self, operands):
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def map_operand(operand):
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if operand is None:
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@ -67,14 +74,13 @@ class DebugInfoEmitter:
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})
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@memoize
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def emit_compile_unit(self, source_buffer, llsubprograms):
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def emit_compile_unit(self, source_buffer):
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return self.emit_debug_info("DICompileUnit", {
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"language": ll.DIToken("DW_LANG_Python"),
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"file": self.emit_file(source_buffer),
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"producer": "ARTIQ",
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"runtimeVersion": 0,
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"emissionKind": 2, # full=1, lines only=2
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"subprograms": self.emit_metadata(llsubprograms)
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}, is_distinct=True)
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@memoize
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@ -86,21 +92,26 @@ class DebugInfoEmitter:
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@memoize
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def emit_subprogram(self, func, llfunc):
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source_buffer = func.loc.source_buffer
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if self.llcompileunit is None:
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self.llcompileunit = self.emit_compile_unit(source_buffer)
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llcompileunits = self.llmodule.add_named_metadata('llvm.dbg.cu')
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llcompileunits.add(self.llcompileunit)
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display_name = "{}{}".format(func.name, types.TypePrinter().name(func.type))
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llsubprogram = self.emit_debug_info("DISubprogram", {
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return self.emit_debug_info("DISubprogram", {
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"name": func.name,
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"linkageName": llfunc.name,
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"type": self.emit_subroutine_type(func.type),
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"file": self.emit_file(source_buffer),
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"line": func.loc.line(),
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"unit": self.llcompileunit,
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"scope": self.emit_file(source_buffer),
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"scopeLine": func.loc.line(),
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"isLocal": func.is_internal,
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"isDefinition": True,
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"variables": self.emit_metadata([])
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}, is_distinct=True)
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self.llsubprograms.append(llsubprogram)
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return llsubprogram
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@memoize
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def emit_loc(self, loc, scope):
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@ -110,18 +121,6 @@ class DebugInfoEmitter:
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"scope": scope
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})
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def finalize(self, source_buffer):
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llident = self.llmodule.add_named_metadata('llvm.ident')
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llident.add(self.emit_metadata(["ARTIQ"]))
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llflags = self.llmodule.add_named_metadata('llvm.module.flags')
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llflags.add(self.emit_metadata([2, "Debug Info Version", 3]))
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llflags.add(self.emit_metadata([2, "Dwarf Version", 4]))
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llcompile_units = self.llmodule.add_named_metadata('llvm.dbg.cu')
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llcompile_units.add(self.emit_compile_unit(source_buffer, tuple(self.llsubprograms)))
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class LLVMIRGenerator:
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def __init__(self, engine, module_name, target, embedding_map):
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self.engine = engine
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@ -410,9 +409,6 @@ class LLVMIRGenerator:
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for func in functions:
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self.process_function(func)
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if any(functions):
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self.debug_info_emitter.finalize(functions[0].loc.source_buffer)
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if attribute_writeback and self.embedding_map is not None:
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self.emit_attribute_writeback()
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@ -18,7 +18,7 @@ requirements:
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- binutils-or1k-linux
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run:
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- python >=3.5.2
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- llvmlite-artiq 0.10.0.dev py35_24
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- llvmlite-artiq 0.11.0.dev py35_25
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- lit
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- outputcheck
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- scipy
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