From 0d708cd61a83e74ea4c73d95267b999bf26138a3 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:59:09 +0800 Subject: [PATCH] compiler/target: split RISCV target into float/non-float --- artiq/compiler/targets.py | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/artiq/compiler/targets.py b/artiq/compiler/targets.py index e908ce38a..dc5b68be8 100644 --- a/artiq/compiler/targets.py +++ b/artiq/compiler/targets.py @@ -98,7 +98,8 @@ class Target: lltarget = llvm.Target.from_triple(self.triple) llmachine = lltarget.create_target_machine( features=",".join(["+{}".format(f) for f in self.features]), - reloc="pic", codemodel="default") + reloc="pic", codemodel="default", + abiname="ilp32d" if isinstance(self, RV32GTarget) else "") llmachine.set_asm_verbosity(True) return llmachine @@ -252,7 +253,7 @@ class NativeTarget(Target): self.triple = llvm.get_default_triple() host_data_layout = str(llvm.targets.Target.from_default_triple().create_target_machine().target_data) -class RISCVTarget(Target): +class RV32IMATarget(Target): triple = "riscv32-unknown-linux" data_layout = "e-m:e-p:32:32-i64:64-n32-S128" features = ["m", "a"] @@ -264,6 +265,18 @@ class RISCVTarget(Target): tool_addr2line = "llvm-addr2line" tool_cxxfilt = "llvm-cxxfilt" +class RV32GTarget(Target): + triple = "riscv32-unknown-linux" + data_layout = "e-m:e-p:32:32-i64:64-n32-S128" + features = ["m", "a", "f", "d"] + print_function = "core_log" + now_pinning = True + + tool_ld = "ld.lld" + tool_strip = "llvm-strip" + tool_addr2line = "llvm-addr2line" + tool_cxxfilt = "llvm-cxxfilt" + class CortexA9Target(Target): triple = "armv7-unknown-linux-gnueabihf" data_layout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"