diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 04c990343..ba9c8da5f 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -239,192 +239,6 @@ class SUServo(StandaloneBase): pads.clkout, self.crg.cd_sys.clk) -class PTB(StandaloneBase): - """PTB Kasli variant - - F.k.a. ptb-schmidt, ptb-mehlstaeubler, ptb-huntemann-11, ptb-huntemann-19, - and ufr-warring in the artiq-setup repository - """ - def __init__(self, hw_rev=None, **kwargs): - if hw_rev is None: - hw_rev = "v1.1" - StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) - - self.config["SI5324_AS_SYNTHESIZER"] = None - # self.config["SI5324_EXT_REF"] = None - self.config["RTIO_FREQUENCY"] = "125.0" - if hw_rev == "v1.0": - # EEM clock fan-out from Si5324, not MMCX - self.comb += self.platform.request("clk_sel").eq(1) - - self.rtio_channels = [] - eem.DIO.add_std(self, 0, - ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) - eem.DIO.add_std(self, 1, - ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) - eem.DIO.add_std(self, 2, - ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) - eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X) - eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X) - eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X) - - for i in (1, 2): - sfp_ctl = self.platform.request("sfp_ctl", i) - phy = ttl_simple.Output(sfp_ctl.led) - self.submodules += phy - self.rtio_channels.append(rtio.Channel.from_phy(phy)) - - eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) - - self.config["HAS_RTIO_LOG"] = None - self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) - self.rtio_channels.append(rtio.LogChannel()) - - self.add_rtio(self.rtio_channels) - - -class PTB2(StandaloneBase): - """PTB Kasli variant with Urukul1 SYNC and external reference clock""" - def __init__(self, hw_rev=None, **kwargs): - if hw_rev is None: - hw_rev = "v1.1" - StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) - - self.config["SI5324_AS_SYNTHESIZER"] = None - self.config["SI5324_EXT_REF"] = None - self.config["EXT_REF_FREQUENCY"] = "100.0" - self.config["RTIO_FREQUENCY"] = "125.0" - if hw_rev == "v1.0": - # EEM clock fan-out from Si5324, not MMCX - self.comb += self.platform.request("clk_sel").eq(1) - - self.rtio_channels = [] - eem.DIO.add_std(self, 0, - ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) - eem.DIO.add_std(self, 1, - ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) - eem.DIO.add_std(self, 2, - ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) - eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X) - eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X, - ttl_simple.ClockGen) - eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X, - ttl_simple.ClockGen) - - for i in (1, 2): - sfp_ctl = self.platform.request("sfp_ctl", i) - phy = ttl_simple.Output(sfp_ctl.led) - self.submodules += phy - self.rtio_channels.append(rtio.Channel.from_phy(phy)) - - eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) - - self.config["HAS_RTIO_LOG"] = None - self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) - self.rtio_channels.append(rtio.LogChannel()) - - self.add_rtio(self.rtio_channels) - - -class HUB(StandaloneBase): - """HUB Kasli variant - - F.k.a. hub-krutzik, luh-ospelkaus-13, and luh-ospelkaus-14 - in the artiq-setup repository - """ - def __init__(self, hw_rev=None, **kwargs): - if hw_rev is None: - hw_rev = "v1.1" - StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) - - self.config["SI5324_AS_SYNTHESIZER"] = None - # self.config["SI5324_EXT_REF"] = None - self.config["RTIO_FREQUENCY"] = "125.0" - if hw_rev == "v1.0": - # EEM clock fan-out from Si5324, not MMCX - self.comb += self.platform.request("clk_sel").eq(1) - - self.rtio_channels = [] - eem.DIO.add_std(self, 0, - ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) - eem.DIO.add_std(self, 1, - ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) - eem.DIO.add_std(self, 2, - ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) - eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X) - eem.Urukul.add_std(self, 4, None, ttl_serdes_7series.Output_8X, - ttl_simple.ClockGen) - eem.Urukul.add_std(self, 5, None, ttl_serdes_7series.Output_8X, - ttl_simple.ClockGen) - eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X, - ttl_simple.ClockGen) - - for i in (1, 2): - sfp_ctl = self.platform.request("sfp_ctl", i) - phy = ttl_simple.Output(sfp_ctl.led) - self.submodules += phy - self.rtio_channels.append(rtio.Channel.from_phy(phy)) - - eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) - - self.config["HAS_RTIO_LOG"] = None - self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) - self.rtio_channels.append(rtio.LogChannel()) - - self.add_rtio(self.rtio_channels) - - -class LUH(StandaloneBase): - """LUH Kasli variant - - F.k.a. luh-ospelkaus-16, luh-ospelkaus-18 in the artiq-setup repository - """ - def __init__(self, hw_rev=None, **kwargs): - if hw_rev is None: - hw_rev = "v1.1" - StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) - - self.config["SI5324_AS_SYNTHESIZER"] = None - # self.config["SI5324_EXT_REF"] = None - self.config["RTIO_FREQUENCY"] = "125.0" - if hw_rev == "v1.0": - # EEM clock fan-out from Si5324, not MMCX - self.comb += self.platform.request("clk_sel").eq(1) - - self.rtio_channels = [] - self.grabber_csr_group = [] - eem.DIO.add_std(self, 0, - ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) - eem.DIO.add_std(self, 1, - ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) - eem.DIO.add_std(self, 2, - ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) - eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X) - eem.Urukul.add_std(self, 4, None, ttl_serdes_7series.Output_8X, - ttl_simple.ClockGen) - eem.Urukul.add_std(self, 5, None, ttl_serdes_7series.Output_8X, - ttl_simple.ClockGen) - eem.Grabber.add_std(self, 6) - - for i in (1, 2): - sfp_ctl = self.platform.request("sfp_ctl", i) - phy = ttl_simple.Output(sfp_ctl.led) - self.submodules += phy - self.rtio_channels.append(rtio.Channel.from_phy(phy)) - - eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) - - self.config["HAS_RTIO_LOG"] = None - self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) - self.rtio_channels.append(rtio.LogChannel()) - - self.add_rtio(self.rtio_channels) - self.config["HAS_GRABBER"] = None - self.add_csr_group("grabber", self.grabber_csr_group) - self.platform.add_false_path_constraints( - self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk) - - class Tester(StandaloneBase): """ Configuration for CI tests. Contains the maximum number of different EEMs. @@ -909,7 +723,7 @@ class VLBAISatellite(SatelliteBase): VARIANTS = {cls.__name__.lower(): cls for cls in [ - Opticlock, SUServo, PTB, PTB2, HUB, LUH, + Opticlock, SUServo, VLBAIMaster, VLBAISatellite, Tester, Master, Satellite]}