forked from M-Labs/artiq
suservo: clean up and beautify example
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@ -16,11 +16,12 @@ class SUServo(EnvExperiment):
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mask = 1 << 18 - 1
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for name, val in zip("ftw1 b1 pow cfg offset a1 ftw0 b0".split(), d):
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val = -(val & mask) + (val & ~mask)
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print(name, hex(val), val)
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print("{}: {:x} = {}".format(name, val, val))
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@rpc(flags={"async"})
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def p1(self, adc, asf, st):
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print("{:10s}".format("#"*int(adc*10)))
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print("ADC: {:10s}, ASF: {:10s}, clipped: {}".format(
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"#"*int(adc), "#"*int(asf*10), (st >> 8) & 1), end="\r")
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@kernel
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def init(self):
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@ -40,28 +41,43 @@ class SUServo(EnvExperiment):
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# Servo is done and disabled
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assert self.suservo0.get_status() & 0xff == 2
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# set up profile 0 on channel 0
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# set up profile 0 on channel 0:
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delay(100*us)
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self.suservo0_ch0.set_y(0, 0.)
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self.suservo0_ch0.set_y(
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profile=0,
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y=0. # clear integrator
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)
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self.suservo0_ch0.set_iir(
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profile=0, adc=7, gain=-.1, corner=7000*Hz, limit=0., delay=0.)
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profile=0,
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adc=7, # take data from Sampler channel 7
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gain=-.1, # -0.1 P gain
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corner=70*Hz, # very low corner frequency
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limit=0., # unlimited integrator gain
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delay=0. # no IIR update delay after enabling
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)
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# setpoint 0.5 (5 V with above PGIA gain setting)
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# 71 MHz
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# 0 phase
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self.suservo0_ch0.set_dds(
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profile=0, offset=-.5, frequency=71*MHz, phase=0.)
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# enable channel
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profile=0,
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offset=-.5, # 5 V with above PGIA settings
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frequency=71*MHz,
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phase=0.)
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# enable RF, IIR updates and profile 0
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self.suservo0_ch0.set(en_out=1, en_iir=1, profile=0)
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# enable servo iterations
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# enable global servo iterations
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self.suservo0.set_config(enable=1)
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# check servo enabled
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assert self.suservo0.get_status() & 0x01 == 1
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delay(10*us)
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# read back profile data
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data = [0] * 8
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self.suservo0_ch0.get_profile_mu(0, data)
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self.p(data)
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delay(10*ms)
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# check servo enabled
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assert self.suservo0.get_status() & 0x01 == 1
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delay(10*us)
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while True:
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self.suservo0.set_config(0)
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delay(10*us)
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@ -73,7 +89,7 @@ class SUServo(EnvExperiment):
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delay(10*us)
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self.suservo0.set_config(1)
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self.p1(v, w, x)
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delay(200*ms)
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delay(20*ms)
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@kernel
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def led(self):
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