forked from M-Labs/artiq
unify rtio/drtio kernel interface
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07ad00c1ca
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0c1a76d668
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@ -4,24 +4,7 @@ from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.cdc import RTIOCounter
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class _KernelCSRs(AutoCSR):
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def __init__(self):
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# chan_sel must be written at least 1 cycle before we
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# and held stable until the transaction is complete.
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# timestamp must be written at least 1 cycle before we.
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self.chan_sel = CSRStorage(16)
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self.o_data = CSRStorage(64)
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self.o_address = CSRStorage(16)
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self.o_timestamp = CSRStorage(64)
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self.o_we = CSR()
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self.o_status = CSRStatus(3)
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self.o_underflow_reset = CSR()
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self.o_sequence_error_reset = CSR()
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self.counter = CSRStatus(64)
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self.counter_update = CSR()
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from artiq.gateware.rtio.kernel_csrs import KernelCSRs
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class _CSRs(AutoCSR):
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@ -45,7 +28,7 @@ class _CSRs(AutoCSR):
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class RTController(Module):
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def __init__(self, rt_packets, channel_count, fine_ts_width):
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self.kcsrs = _KernelCSRs()
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self.kcsrs = KernelCSRs()
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self.csrs = _CSRs()
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chan_sel = Signal(16)
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@ -5,9 +5,9 @@ from migen import *
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from migen.genlib.record import Record
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import rtlink
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from artiq.gateware.rtio.kernel_csrs import KernelCSRs
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from artiq.gateware.rtio.cdc import *
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@ -265,36 +265,6 @@ class LogChannel:
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self.overrides = []
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class _KernelCSRs(AutoCSR):
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def __init__(self, chan_sel_width,
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data_width, address_width, full_ts_width):
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self.reset = CSRStorage(reset=1)
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self.reset_phy = CSRStorage(reset=1)
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self.chan_sel = CSRStorage(chan_sel_width)
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if data_width:
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self.o_data = CSRStorage(data_width)
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if address_width:
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self.o_address = CSRStorage(address_width)
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self.o_timestamp = CSRStorage(full_ts_width)
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self.o_we = CSR()
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self.o_status = CSRStatus(5)
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self.o_underflow_reset = CSR()
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self.o_sequence_error_reset = CSR()
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self.o_collision_reset = CSR()
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self.o_busy_reset = CSR()
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if data_width:
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self.i_data = CSRStatus(data_width)
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self.i_timestamp = CSRStatus(full_ts_width)
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self.i_re = CSR()
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self.i_status = CSRStatus(2)
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self.i_overflow_reset = CSR()
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self.counter = CSRStatus(full_ts_width)
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self.counter_update = CSR()
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class RTIO(Module):
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def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
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data_width = max(rtlink.get_data_width(c.interface)
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@ -308,10 +278,7 @@ class RTIO(Module):
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self.address_width = address_width
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self.fine_ts_width = fine_ts_width
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# CSRs
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self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
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data_width, address_width,
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full_ts_width)
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self.kcsrs = KernelCSRs()
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# Clocking/Reset
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# Create rsys, rio and rio_phy domains based on sys and rtio
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@ -0,0 +1,27 @@
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from misoc.interconnect.csr import *
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class KernelCSRs(AutoCSR):
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def __init__(self):
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self.reset = CSRStorage(reset=1)
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self.reset_phy = CSRStorage(reset=1)
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self.chan_sel = CSRStorage(16)
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self.o_data = CSRStorage(32)
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self.o_address = CSRStorage(16)
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self.o_timestamp = CSRStorage(64)
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self.o_we = CSR()
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self.o_status = CSRStatus(5)
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self.o_underflow_reset = CSR()
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self.o_sequence_error_reset = CSR()
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self.o_collision_reset = CSR()
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self.o_busy_reset = CSR()
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self.i_data = CSRStatus(32)
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self.i_timestamp = CSRStatus(64)
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self.i_re = CSR()
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self.i_status = CSRStatus(2)
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self.i_overflow_reset = CSR()
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self.counter = CSRStatus(64)
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self.counter_update = CSR()
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