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sawg: use new rtio_output() API

This commit is contained in:
Sebastien Bourdeauducq 2018-11-08 20:16:30 +08:00
parent bec25cbaa0
commit 0bee43aa58
2 changed files with 13 additions and 13 deletions

View File

@ -10,7 +10,7 @@ Output event replacement is supported except on the configuration channel.
from artiq.language.types import TInt32, TFloat from artiq.language.types import TInt32, TFloat
from numpy import int32, int64 from numpy import int32, int64
from artiq.language.core import kernel, now_mu from artiq.language.core import kernel
from artiq.coredevice.spline import Spline from artiq.coredevice.spline import Spline
from artiq.coredevice.rtio import rtio_output from artiq.coredevice.rtio import rtio_output
@ -69,7 +69,7 @@ class Config:
``t_sawg_spline/t_rtio_coarse = div + 1``. Default: ``0``. ``t_sawg_spline/t_rtio_coarse = div + 1``. Default: ``0``.
:param n: Current value of the counter. Default: ``0``. :param n: Current value of the counter. Default: ``0``.
""" """
rtio_output(now_mu(), self.channel, _SAWG_DIV, div | (n << 16)) rtio_output((self.channel << 8) | _SAWG_DIV, div | (n << 16))
delay_mu(self._rtio_interval) delay_mu(self._rtio_interval)
@kernel @kernel
@ -108,7 +108,7 @@ class Config:
:param clr2: Auto-clear phase accumulator of the ``phase2``/ :param clr2: Auto-clear phase accumulator of the ``phase2``/
``frequency2`` DDS. Default: ``True`` ``frequency2`` DDS. Default: ``True``
""" """
rtio_output(now_mu(), self.channel, _SAWG_CLR, clr0 | rtio_output((self.channel << 8) | _SAWG_CLR, clr0 |
(clr1 << 1) | (clr2 << 2)) (clr1 << 1) | (clr2 << 2))
delay_mu(self._rtio_interval) delay_mu(self._rtio_interval)
@ -135,7 +135,7 @@ class Config:
DUC-DDS data of this SAWG's *buddy* channel to *this* DAC DUC-DDS data of this SAWG's *buddy* channel to *this* DAC
channel. Default: ``0``. channel. Default: ``0``.
""" """
rtio_output(now_mu(), self.channel, _SAWG_IQ_EN, i_enable | rtio_output((self.channel << 8) | _SAWG_IQ_EN, i_enable |
(q_enable << 1)) (q_enable << 1))
delay_mu(self._rtio_interval) delay_mu(self._rtio_interval)
@ -151,25 +151,25 @@ class Config:
.. seealso:: :meth:`set_duc_max` .. seealso:: :meth:`set_duc_max`
""" """
rtio_output(now_mu(), self.channel, _SAWG_DUC_MAX, limit) rtio_output((self.channel << 8) | _SAWG_DUC_MAX, limit)
delay_mu(self._rtio_interval) delay_mu(self._rtio_interval)
@kernel @kernel
def set_duc_min_mu(self, limit: TInt32): def set_duc_min_mu(self, limit: TInt32):
""".. seealso:: :meth:`set_duc_max_mu`""" """.. seealso:: :meth:`set_duc_max_mu`"""
rtio_output(now_mu(), self.channel, _SAWG_DUC_MIN, limit) rtio_output((self.channel << 8) | _SAWG_DUC_MIN, limit)
delay_mu(self._rtio_interval) delay_mu(self._rtio_interval)
@kernel @kernel
def set_out_max_mu(self, limit: TInt32): def set_out_max_mu(self, limit: TInt32):
""".. seealso:: :meth:`set_duc_max_mu`""" """.. seealso:: :meth:`set_duc_max_mu`"""
rtio_output(now_mu(), self.channel, _SAWG_OUT_MAX, limit) rtio_output((self.channel << 8) | _SAWG_OUT_MAX, limit)
delay_mu(self._rtio_interval) delay_mu(self._rtio_interval)
@kernel @kernel
def set_out_min_mu(self, limit: TInt32): def set_out_min_mu(self, limit: TInt32):
""".. seealso:: :meth:`set_duc_max_mu`""" """.. seealso:: :meth:`set_duc_max_mu`"""
rtio_output(now_mu(), self.channel, _SAWG_OUT_MIN, limit) rtio_output((self.channel << 8) | _SAWG_OUT_MIN, limit)
delay_mu(self._rtio_interval) delay_mu(self._rtio_interval)
@kernel @kernel

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@ -1,5 +1,5 @@
from numpy import int32, int64 from numpy import int32, int64
from artiq.language.core import kernel, now_mu, portable, delay from artiq.language.core import kernel, portable, delay
from artiq.coredevice.rtio import rtio_output, rtio_output_wide from artiq.coredevice.rtio import rtio_output, rtio_output_wide
from artiq.language.types import TInt32, TInt64, TFloat from artiq.language.types import TInt32, TInt64, TFloat
@ -65,7 +65,7 @@ class Spline:
:param value: Spline value in integer machine units. :param value: Spline value in integer machine units.
""" """
rtio_output(now_mu(), self.channel, 0, value) rtio_output(self.channel << 8, value)
@kernel(flags={"fast-math"}) @kernel(flags={"fast-math"})
def set(self, value: TFloat): def set(self, value: TFloat):
@ -76,9 +76,9 @@ class Spline:
if self.width > 32: if self.width > 32:
l = [int32(0)] * 2 l = [int32(0)] * 2
self.pack_coeff_mu([self.to_mu64(value)], l) self.pack_coeff_mu([self.to_mu64(value)], l)
rtio_output_wide(now_mu(), self.channel, 0, l) rtio_output_wide(self.channel << 8, l)
else: else:
rtio_output(now_mu(), self.channel, 0, self.to_mu(value)) rtio_output(self.channel << 8, self.to_mu(value))
@kernel @kernel
def set_coeff_mu(self, value): # TList(TInt32) def set_coeff_mu(self, value): # TList(TInt32)
@ -86,7 +86,7 @@ class Spline:
:param value: Spline packed raw values. :param value: Spline packed raw values.
""" """
rtio_output_wide(now_mu(), self.channel, 0, value) rtio_output_wide(self.channel << 8, value)
@portable(flags={"fast-math"}) @portable(flags={"fast-math"})
def pack_coeff_mu(self, coeff, packed): # TList(TInt64), TList(TInt32) def pack_coeff_mu(self, coeff, packed): # TList(TInt64), TList(TInt32)