sawg: use new rtio_output() API

artiq/coredevice/sawg.py

@@ -10,7 +10,7 @@ Output event replacement is supported except on the configuration channel.
 
 from artiq.language.types import TInt32, TFloat
 from numpy import int32, int64
-from artiq.language.core import kernel, now_mu
+from artiq.language.core import kernel
 from artiq.coredevice.spline import Spline
 from artiq.coredevice.rtio import rtio_output
 
@@ -69,7 +69,7 @@ class Config:
             ``t_sawg_spline/t_rtio_coarse = div + 1``. Default: ``0``.
         :param n: Current value of the counter. Default: ``0``.
         """
-        rtio_output(now_mu(), self.channel, _SAWG_DIV, div | (n << 16))
+        rtio_output((self.channel << 8) | _SAWG_DIV, div | (n << 16))
         delay_mu(self._rtio_interval)
 
     @kernel
@@ -108,7 +108,7 @@ class Config:
         :param clr2: Auto-clear phase accumulator of the ``phase2``/
           ``frequency2`` DDS. Default: ``True``
         """
-        rtio_output(now_mu(), self.channel, _SAWG_CLR, clr0 |
+        rtio_output((self.channel << 8) | _SAWG_CLR, clr0 |
                 (clr1 << 1) | (clr2 << 2))
         delay_mu(self._rtio_interval)
 
@@ -135,7 +135,7 @@ class Config:
               DUC-DDS data of this SAWG's *buddy* channel to *this* DAC
               channel. Default: ``0``.
         """
-        rtio_output(now_mu(), self.channel, _SAWG_IQ_EN, i_enable |
+        rtio_output((self.channel << 8) | _SAWG_IQ_EN, i_enable |
                 (q_enable << 1))
         delay_mu(self._rtio_interval)
 
@@ -151,25 +151,25 @@ class Config:
 
         .. seealso:: :meth:`set_duc_max`
         """
-        rtio_output(now_mu(), self.channel, _SAWG_DUC_MAX, limit)
+        rtio_output((self.channel << 8) | _SAWG_DUC_MAX, limit)
         delay_mu(self._rtio_interval)
 
     @kernel
     def set_duc_min_mu(self, limit: TInt32):
         """.. seealso:: :meth:`set_duc_max_mu`"""
-        rtio_output(now_mu(), self.channel, _SAWG_DUC_MIN, limit)
+        rtio_output((self.channel << 8) | _SAWG_DUC_MIN, limit)
         delay_mu(self._rtio_interval)
 
     @kernel
     def set_out_max_mu(self, limit: TInt32):
         """.. seealso:: :meth:`set_duc_max_mu`"""
-        rtio_output(now_mu(), self.channel, _SAWG_OUT_MAX, limit)
+        rtio_output((self.channel << 8) | _SAWG_OUT_MAX, limit)
         delay_mu(self._rtio_interval)
 
     @kernel
     def set_out_min_mu(self, limit: TInt32):
         """.. seealso:: :meth:`set_duc_max_mu`"""
-        rtio_output(now_mu(), self.channel, _SAWG_OUT_MIN, limit)
+        rtio_output((self.channel << 8) | _SAWG_OUT_MIN, limit)
         delay_mu(self._rtio_interval)
 
     @kernel

artiq/coredevice/spline.py

@@ -1,5 +1,5 @@
 from numpy import int32, int64
-from artiq.language.core import kernel, now_mu, portable, delay
+from artiq.language.core import kernel, portable, delay
 from artiq.coredevice.rtio import rtio_output, rtio_output_wide
 from artiq.language.types import TInt32, TInt64, TFloat
 
@@ -65,7 +65,7 @@ class Spline:
 
         :param value: Spline value in integer machine units.
         """
-        rtio_output(now_mu(), self.channel, 0, value)
+        rtio_output(self.channel << 8, value)
 
     @kernel(flags={"fast-math"})
     def set(self, value: TFloat):
@@ -76,9 +76,9 @@ class Spline:
         if self.width > 32:
             l = [int32(0)] * 2
             self.pack_coeff_mu([self.to_mu64(value)], l)
-            rtio_output_wide(now_mu(), self.channel, 0, l)
+            rtio_output_wide(self.channel << 8, l)
         else:
-            rtio_output(now_mu(), self.channel, 0, self.to_mu(value))
+            rtio_output(self.channel << 8, self.to_mu(value))
 
     @kernel
     def set_coeff_mu(self, value):  # TList(TInt32)
@@ -86,7 +86,7 @@ class Spline:
 
         :param value: Spline packed raw values.
         """
-        rtio_output_wide(now_mu(), self.channel, 0, value)
+        rtio_output_wide(self.channel << 8, value)
 
     @portable(flags={"fast-math"})
     def pack_coeff_mu(self, coeff, packed):  # TList(TInt64), TList(TInt32)