forked from M-Labs/artiq
dma: request RTIO control
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parent
553b8046ff
commit
0b4922e0f4
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@ -301,6 +301,18 @@ extern fn dma_erase(name: CSlice<u8>) {
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send(&DmaEraseRequest(name));
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send(&DmaEraseRequest(name));
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}
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}
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unsafe fn rtio_arb_dma() {
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csr::rtio::arb_req_write(0);
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csr::rtio_dma::arb_req_write(1);
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while csr::rtio_dma::arb_gnt_read() == 0 {}
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}
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unsafe fn rtio_arb_regular() {
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csr::rtio_dma::arb_req_write(0);
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csr::rtio::arb_req_write(1);
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while csr::rtio::arb_gnt_read() == 0 {}
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}
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extern fn dma_playback(timestamp: i64, name: CSlice<u8>) {
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extern fn dma_playback(timestamp: i64, name: CSlice<u8>) {
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let name = str::from_utf8(name.as_ref()).unwrap();
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let name = str::from_utf8(name.as_ref()).unwrap();
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@ -312,8 +324,10 @@ extern fn dma_playback(timestamp: i64, name: CSlice<u8>) {
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csr::rtio_dma::base_address_write(data.as_ptr() as u64);
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csr::rtio_dma::base_address_write(data.as_ptr() as u64);
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csr::rtio_dma::time_offset_write(timestamp as u64);
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csr::rtio_dma::time_offset_write(timestamp as u64);
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rtio_arb_dma();
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csr::rtio_dma::enable_write(1);
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csr::rtio_dma::enable_write(1);
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while csr::rtio_dma::enable_read() != 0 {}
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while csr::rtio_dma::enable_read() != 0 {}
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rtio_arb_regular();
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let status = csr::rtio_dma::error_status_read();
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let status = csr::rtio_dma::error_status_read();
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let timestamp = csr::rtio_dma::error_timestamp_read();
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let timestamp = csr::rtio_dma::error_timestamp_read();
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