From 47191eda91a98cd15de6a43855f63992f2e99e2c Mon Sep 17 00:00:00 2001
From: Robert Jordens <jordens@gmail.com>
Date: Sun, 19 Jul 2015 21:36:51 -0600
Subject: [PATCH] dds monitor: relax timing (for pipistrello)

---
 artiq/gateware/rtio/phy/dds.py | 43 +++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 21 deletions(-)

diff --git a/artiq/gateware/rtio/phy/dds.py b/artiq/gateware/rtio/phy/dds.py
index e9685223d..8568c57e1 100644
--- a/artiq/gateware/rtio/phy/dds.py
+++ b/artiq/gateware/rtio/phy/dds.py
@@ -14,39 +14,40 @@ class _AD9xxx(Module):
 
         # # #
 
+        # buffer the current address/data on the rtlink output
+        current_address = Signal.like(self.rtlink.o.address)
+        current_data = Signal.like(self.rtlink.o.data)
+        self.sync.rio += If(self.rtlink.o.stb,
+                            current_address.eq(self.rtlink.o.address),
+                            current_data.eq(self.rtlink.o.data))
+
         # keep track of the currently selected channel
         current_channel = Signal(max=nchannels)
-        self.sync.rio += If(self.rtlink.o.stb & 
-            (self.rtlink.o.address == 2**flen(pads.a)+1),
-                current_channel.eq(self.rtlink.o.data))
+        self.sync.rio += If(current_address == 2**flen(pads.a) + 1,
+                            current_channel.eq(current_data))
 
         # keep track of frequency tuning words, before they are FUDed
         ftws = [Signal(32) for i in range(nchannels)]
         for c, ftw in enumerate(ftws):
             if flen(pads.d) == 8:
-                for i in range(4):
-                    self.sync.rio += \
-                        If(self.rtlink.o.stb & \
-                            (self.rtlink.o.address == ftw_base+i) & \
-                            (current_channel == c),
-                                ftw[i*8:(i+1)*8].eq(self.rtlink.o.data)
-                        )
+                self.sync.rio += \
+                    If(current_channel == c, [
+                        If(current_address == ftw_base+i,
+                           ftw[i*8:(i+1)*8].eq(current_data))
+                        for i in range(4)])
             elif flen(pads.d) == 16:
-                for i in range(2):
-                    self.sync.rio += \
-                        If(self.rtlink.o.stb & \
-                            (self.rtlink.o.address == ftw_base+2*i) & \
-                            (current_channel == c),
-                                ftw[i*16:(i+1)*16].eq(self.rtlink.o.data)
-                        )
+                self.sync.rio += \
+                    If(current_channel == c, [
+                        If(current_address == ftw_base+2*i,
+                           ftw[i*16:(i+1)*16].eq(current_data))
+                        for i in range(2)])
             else:
                 raise NotImplementedError
 
         # FTW to probe on FUD
-        for c, (probe, ftw) in enumerate(zip(self.probes, ftws)):
-            fud = self.rtlink.o.stb & \
-                (self.rtlink.o.address == 2**flen(pads.a))
-            self.sync.rio += If(fud & (current_channel == c), probe.eq(ftw))
+        self.sync.rio += If(current_address == 2**flen(pads.a), [
+            If(current_channel == c, probe.eq(ftw))
+            for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
 
 
 class AD9858(_AD9xxx):