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kc705_drtio_master: add missing rtio_core CSRs

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Sebastien Bourdeauducq 2016-12-09 19:23:36 +08:00
parent 4422b6902a
commit 0a9f69a3ed
1 changed files with 1 additions and 0 deletions
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artiq/gateware/targets/kc705_drtio_master.py
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@ -100,6 +100,7 @@ class Master(MiniSoC, AMPSoC):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_core = rtio.Core(rtio_channels, 3) self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator() self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if()) self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())