forked from M-Labs/artiq
move i2c to libboard, do bit-banging on comms CPU
This commit is contained in:
parent
3dd9d54b22
commit
082fdaf450
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@ -126,10 +126,6 @@ class DDSError(Exception):
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incorrect.
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"""
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class I2CError(Exception):
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"""Raised with a I2C transaction fails."""
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artiq_builtin = True
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class WatchdogExpired(Exception):
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"""Raised when a watchdog expires."""
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@ -1,11 +1,10 @@
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from artiq.language.core import syscall, kernel
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from artiq.language.types import TBool, TInt32, TNone
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from artiq.coredevice.exceptions import I2CError
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@syscall(flags={"nowrite"})
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def i2c_init(busno: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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class I2CError(Exception):
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"""Raised with a I2C transaction fails."""
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pass
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@syscall(flags={"nounwind", "nowrite"})
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@ -48,7 +47,6 @@ class PCA9548:
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:param channel: channel number (0-7)
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"""
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i2c_init(self.busno)
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i2c_start(self.busno)
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try:
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if not i2c_write(self.busno, self.address):
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@ -60,7 +58,6 @@ class PCA9548:
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@kernel
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def readback(self):
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i2c_init(self.busno)
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i2c_start(self.busno)
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r = 0
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try:
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@ -84,7 +81,6 @@ class TCA6424A:
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@kernel
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def _write24(self, command, value):
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i2c_init(self.busno)
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i2c_start(self.busno)
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try:
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if not i2c_write(self.busno, self.address):
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@ -0,0 +1,136 @@
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use csr;
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use clock;
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fn half_period() { clock::spin_us(100) }
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fn sda_bit(busno: u32) -> u8 { 1 << (2 * busno + 1) }
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fn scl_bit(busno: u32) -> u8 { 1 << (2 * busno) }
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fn sda_i(busno: u32) -> bool {
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unsafe {
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csr::i2c::in_read() & sda_bit(busno) != 0
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}
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}
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fn sda_oe(busno: u32, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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let reg = if oe { reg | sda_bit(busno) } else { reg & !sda_bit(busno) };
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csr::i2c::oe_write(reg)
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}
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}
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fn sda_o(busno: u32, o: bool) {
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unsafe {
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let reg = csr::i2c::out_read();
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let reg = if o { reg | sda_bit(busno) } else { reg & !sda_bit(busno) };
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csr::i2c::out_write(reg)
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}
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}
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fn scl_oe(busno: u32, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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let reg = if oe { reg | scl_bit(busno) } else { reg & !scl_bit(busno) };
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csr::i2c::oe_write(reg)
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}
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}
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fn scl_o(busno: u32, o: bool) {
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unsafe {
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let reg = csr::i2c::out_read();
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let reg = if o { reg | scl_bit(busno) } else { reg & !scl_bit(busno) };
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csr::i2c::out_write(reg)
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}
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}
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pub fn init() {
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for busno in 0..csr::CONFIG_I2C_BUS_COUNT {
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// Set SCL as output, and high level
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scl_o(busno, true);
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scl_oe(busno, true);
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// Prepare a zero level on SDA so that sda_oe pulls it down
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sda_o(busno, false);
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// Release SDA
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sda_oe(busno, false);
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// Check the I2C bus is ready
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half_period();
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half_period();
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if !sda_i(busno) {
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error!("SDA is stuck low on bus #{}", busno)
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}
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}
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}
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pub fn start(busno: u32) {
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// Set SCL high then SDA low
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scl_o(busno, true);
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half_period();
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sda_oe(busno, true);
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half_period();
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}
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pub fn stop(busno: u32) {
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// First, make sure SCL is low, so that the target releases the SDA line
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scl_o(busno, false);
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half_period();
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// Set SCL high then SDA high
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sda_oe(busno, true);
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scl_o(busno, true);
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half_period();
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sda_oe(busno, false);
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half_period();
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}
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pub fn write(busno: u32, data: u8) -> bool {
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// MSB first
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for bit in (0..8).rev() {
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// Set SCL low and set our bit on SDA
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scl_o(busno, false);
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sda_oe(busno, data & (1 << bit) == 0);
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half_period();
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// Set SCL high ; data is shifted on the rising edge of SCL
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scl_o(busno, true);
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half_period();
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}
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// Check ack
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// Set SCL low, then release SDA so that the I2C target can respond
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scl_o(busno, false);
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half_period();
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sda_oe(busno, false);
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// Set SCL high and check for ack
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scl_o(busno, true);
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half_period();
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// returns true if acked (I2C target pulled SDA low)
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!sda_i(busno)
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}
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pub fn read(busno: u32, ack: bool) -> u8 {
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// Set SCL low first, otherwise setting SDA as input may cause a transition
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// on SDA with SCL high which will be interpreted as START/STOP condition.
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scl_o(busno, false);
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half_period(); // make sure SCL has settled low
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sda_oe(busno, false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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scl_o(busno, false);
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half_period();
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// Set SCL high and shift data
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scl_o(busno, true);
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half_period();
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if sda_i(busno) { data |= 1 << bit }
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}
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// Send ack
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// Set SCL low and pull SDA low when acking
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scl_o(busno, false);
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if ack { sda_oe(busno, true) }
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half_period();
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// then set SCL high
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scl_o(busno, true);
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half_period();
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data
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}
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@ -11,6 +11,8 @@ include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
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pub mod spr;
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pub mod irq;
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pub mod clock;
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#[cfg(has_i2c)]
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pub mod i2c;
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#[cfg(has_ad9516)]
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#[allow(dead_code)]
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mod ad9516_reg;
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@ -106,14 +106,8 @@ static mut API: &'static [(&'static str, *const ())] = &[
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api!(rtio_input_timestamp = ::rtio::input_timestamp),
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api!(rtio_input_data = ::rtio::input_data),
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#[cfg(has_i2c)]
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api!(i2c_init = ::i2c::init),
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#[cfg(has_i2c)]
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api!(i2c_start = ::i2c::start),
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#[cfg(has_i2c)]
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api!(i2c_stop = ::i2c::stop),
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#[cfg(has_i2c)]
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api!(i2c_write = ::i2c::write),
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#[cfg(has_i2c)]
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api!(i2c_read = ::i2c::read),
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api!(i2c_start = ::i2c_start),
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api!(i2c_stop = ::i2c_stop),
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api!(i2c_write = ::i2c_write),
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api!(i2c_read = ::i2c_read),
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];
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@ -1,176 +0,0 @@
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use board::csr;
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fn half_period() {
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unsafe {
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csr::timer_kernel::en_write(0);
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csr::timer_kernel::load_write(csr::CONFIG_CLOCK_FREQUENCY/10000);
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csr::timer_kernel::reload_write(0);
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csr::timer_kernel::en_write(1);
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csr::timer_kernel::update_value_write(1);
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while csr::timer_kernel::value_read() != 0 {
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csr::timer_kernel::update_value_write(1)
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}
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}
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}
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#[cfg(has_i2c)]
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mod imp {
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use board::csr;
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fn sda_bit(busno: u32) -> u32 { 1 << (2 * busno + 1) }
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fn scl_bit(busno: u32) -> u32 { 1 << (2 * busno) }
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pub fn sda_i(busno: u32) -> bool {
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unsafe {
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if busno >= csr::CONFIG_I2C_BUS_COUNT {
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true
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} else {
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csr::i2c::in_read() & sda_bit(busno) != 0
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}
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}
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}
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pub fn sda_oe(busno: u32, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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let reg = if oe { reg | sda_bit(busno) } else { reg & !sda_bit(busno) };
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csr::i2c::oe_write(reg);
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}
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}
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pub fn sda_o(busno: u32, o: bool) {
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unsafe {
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let reg = csr::i2c::out_read();
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let reg = if o { reg | sda_bit(busno) } else { reg & !sda_bit(busno) };
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csr::i2c::out_write(reg)
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}
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}
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pub fn scl_oe(busno: u32, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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let reg = if oe { reg | scl_bit(busno) } else { reg & !scl_bit(busno) };
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csr::i2c::oe_write(reg)
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}
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}
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pub fn scl_o(busno: u32, o: bool) {
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unsafe {
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let reg = csr::i2c::out_read();
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let reg = if o { reg | scl_bit(busno) } else { reg & !scl_bit(busno) };
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csr::i2c::out_write(reg)
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}
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}
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}
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#[cfg(not(has_i2c))]
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mod imp {
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pub fn sda_i(busno: u32) -> bool { true }
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pub fn sda_oe(busno: u32, oe: bool) {}
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pub fn sda_o(busno: u32, o: bool) {}
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pub fn scl_oe(busno: u32, oe: bool) {}
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pub fn scl_o(busno: u32, o: bool) {}
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}
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use self::imp::*;
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pub extern fn init(busno: i32) {
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let busno = busno as u32;
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// Set SCL as output, and high level
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scl_o(busno, true);
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scl_oe(busno, true);
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// Prepare a zero level on SDA so that sda_oe pulls it down
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sda_o(busno, false);
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// Release SDA
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sda_oe(busno, false);
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// Check the I2C bus is ready
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half_period();
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half_period();
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if !sda_i(busno) {
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artiq_raise!("I2CError", "SDA is stuck low")
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}
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}
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pub extern fn start(busno: i32) {
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let busno = busno as u32;
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// Set SCL high then SDA low
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scl_o(busno, true);
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half_period();
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sda_oe(busno, true);
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half_period();
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}
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pub extern fn stop(busno: i32) {
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let busno = busno as u32;
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// First, make sure SCL is low, so that the target releases the SDA line
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scl_o(busno, false);
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half_period();
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// Set SCL high then SDA high
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sda_oe(busno, true);
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scl_o(busno, true);
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half_period();
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sda_oe(busno, false);
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half_period();
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}
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pub extern fn write(busno: i32, data: i8) -> bool {
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let (busno, data) = (busno as u32, data as u8);
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// MSB first
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for bit in (0..8).rev() {
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// Set SCL low and set our bit on SDA
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scl_o(busno, false);
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sda_oe(busno, data & (1 << bit) == 0);
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half_period();
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// Set SCL high ; data is shifted on the rising edge of SCL
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scl_o(busno, true);
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half_period();
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}
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// Check ack
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// Set SCL low, then release SDA so that the I2C target can respond
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scl_o(busno, false);
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half_period();
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sda_oe(busno, false);
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// Set SCL high and check for ack
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scl_o(busno, true);
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half_period();
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// returns true if acked (I2C target pulled SDA low)
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!sda_i(busno)
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}
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pub extern fn read(busno: i32, ack: bool) -> i8 {
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let busno = busno as u32;
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// Set SCL low first, otherwise setting SDA as input may cause a transition
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// on SDA with SCL high which will be interpreted as START/STOP condition.
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scl_o(busno, false);
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half_period(); // make sure SCL has settled low
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sda_oe(busno, false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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scl_o(busno, false);
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half_period();
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// Set SCL high and shift data
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scl_o(busno, true);
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half_period();
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if sda_i(busno) { data |= 1 << bit }
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}
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// Send ack
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// Set SCL low and pull SDA low when acking
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scl_o(busno, false);
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if ack { sda_oe(busno, true) }
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half_period();
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// then set SCL high
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scl_o(busno, true);
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half_period();
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data as i8
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}
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@ -48,8 +48,6 @@ macro_rules! artiq_raise {
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}
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mod rtio;
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#[cfg(has_i2c)]
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mod i2c;
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use core::{mem, ptr, slice, str};
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use std::io::Cursor;
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|
@ -243,6 +241,24 @@ extern fn cache_put(key: *const u8, list: ArtiqList<i32>) {
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})
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}
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extern fn i2c_start(busno: i32) {
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send(&I2CStartRequest { busno: busno as u32 });
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}
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extern fn i2c_stop(busno: i32) {
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send(&I2CStopRequest { busno: busno as u32 });
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}
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extern fn i2c_write(busno: i32, data: i8) -> bool {
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send(&I2CWriteRequest { busno: busno as u32, data: data as u8 });
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recv!(&I2CWriteReply { ack } => ack)
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}
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extern fn i2c_read(busno: i32, ack: bool) -> i8 {
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send(&I2CReadRequest { busno: busno as u32, ack: ack });
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recv!(&I2CReadReply { data } => data) as i8
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}
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unsafe fn attribute_writeback(typeinfo: *const ()) {
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struct Attr {
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offset: usize,
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|
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@ -57,6 +57,13 @@ pub enum Message<'a> {
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CachePutRequest { key: &'a str, value: &'a [i32] },
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CachePutReply { succeeded: bool },
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I2CStartRequest { busno: u32 },
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I2CStopRequest { busno: u32 },
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I2CWriteRequest { busno: u32, data: u8 },
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I2CWriteReply { ack: bool },
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I2CReadRequest { busno: u32, ack: bool },
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I2CReadReply { data: u8 },
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Log(fmt::Arguments<'a>),
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LogSlice(&'a str)
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}
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|
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|
@ -120,6 +120,8 @@ pub unsafe extern fn rust_main() {
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}
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info!("continuing boot");
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#[cfg(has_i2c)]
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board::i2c::init();
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#[cfg(has_ad9516)]
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board::ad9516::init().unwrap();
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#[cfg(has_converter_spi)]
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|
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|
@ -422,6 +422,44 @@ fn process_kern_message(waiter: Waiter,
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kern_send(waiter, &kern::CachePutReply { succeeded: succeeded })
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}
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#[cfg(has_i2c)]
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&kern::I2CStartRequest { busno } => {
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board::i2c::start(busno);
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kern_acknowledge()
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}
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#[cfg(has_i2c)]
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&kern::I2CStopRequest { busno } => {
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board::i2c::stop(busno);
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||||
kern_acknowledge()
|
||||
}
|
||||
#[cfg(has_i2c)]
|
||||
&kern::I2CWriteRequest { busno, data } => {
|
||||
let ack = board::i2c::write(busno, data);
|
||||
kern_send(waiter, &kern::I2CWriteReply { ack: ack })
|
||||
}
|
||||
#[cfg(has_i2c)]
|
||||
&kern::I2CReadRequest { busno, ack } => {
|
||||
let data = board::i2c::read(busno, ack);
|
||||
kern_send(waiter, &kern::I2CReadReply { data: data })
|
||||
}
|
||||
|
||||
#[cfg(not(has_i2c))]
|
||||
&kern::I2CStartRequest { .. } => {
|
||||
kern_acknowledge()
|
||||
}
|
||||
#[cfg(not(has_i2c))]
|
||||
&kern::I2CStopRequest { .. } => {
|
||||
kern_acknowledge()
|
||||
}
|
||||
#[cfg(not(has_i2c))]
|
||||
&kern::I2CWriteRequest { .. } => {
|
||||
kern_send(waiter, &kern::I2CWriteReply { ack: false })
|
||||
}
|
||||
#[cfg(not(has_i2c))]
|
||||
&kern::I2CReadRequest { .. } => {
|
||||
kern_send(waiter, &kern::I2CReadReply { data: 0xff })
|
||||
}
|
||||
|
||||
&kern::RunFinished => {
|
||||
unsafe { kernel::stop() }
|
||||
session.kernel_state = KernelState::Absent;
|
||||
|
|
|
@ -36,9 +36,6 @@ class AMPSoC:
|
|||
self.add_memory_region("mailbox",
|
||||
self.mem_map["mailbox"] | 0x80000000, 4)
|
||||
|
||||
self.submodules.timer_kernel = timer.Timer()
|
||||
self.register_kernel_cpu_csrdevice("timer_kernel")
|
||||
|
||||
def register_kernel_cpu_csrdevice(self, name, csrs=None):
|
||||
if csrs is None:
|
||||
csrs = getattr(self, name).get_csrs()
|
||||
|
|
|
@ -100,10 +100,8 @@ _ams101_dac = [
|
|||
|
||||
class _NIST_Ions(MiniSoC, AMPSoC):
|
||||
mem_map = {
|
||||
"timer_kernel": 0x10000000,
|
||||
"rtio": 0x20000000,
|
||||
"rtio_dma": 0x30000000,
|
||||
"i2c": 0x50000000,
|
||||
"mailbox": 0x70000000
|
||||
}
|
||||
mem_map.update(MiniSoC.mem_map)
|
||||
|
@ -134,7 +132,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
|
|||
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.register_kernel_cpu_csrdevice("i2c")
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
|
||||
self.config["HAS_DDS"] = None
|
||||
|
|
|
@ -20,7 +20,6 @@ from artiq import __version__ as artiq_version
|
|||
|
||||
class Master(MiniSoC, AMPSoC):
|
||||
mem_map = {
|
||||
"timer_kernel": 0x10000000,
|
||||
"rtio": 0x20000000,
|
||||
"rtio_dma": 0x30000000,
|
||||
"drtio_aux": 0x50000000,
|
||||
|
|
|
@ -156,10 +156,8 @@ class AD9154(Module, AutoCSR):
|
|||
|
||||
class Phaser(MiniSoC, AMPSoC):
|
||||
mem_map = {
|
||||
"timer_kernel": 0x10000000,
|
||||
"rtio": 0x20000000,
|
||||
# "rtio_dma": 0x30000000,
|
||||
"i2c": 0x30000000,
|
||||
"mailbox": 0x70000000,
|
||||
"ad9154": 0x50000000,
|
||||
}
|
||||
|
@ -188,7 +186,7 @@ class Phaser(MiniSoC, AMPSoC):
|
|||
|
||||
i2c = platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.register_kernel_cpu_csrdevice("i2c")
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
|
||||
ad9154_spi = platform.request("ad9154_spi")
|
||||
|
|
|
@ -149,7 +149,6 @@ _ttl_io = [
|
|||
|
||||
class Demo(BaseSoC, AMPSoC):
|
||||
mem_map = {
|
||||
"timer_kernel": 0x10000000, # (shadow @0x90000000)
|
||||
"rtio": 0x20000000, # (shadow @0xa0000000)
|
||||
"mailbox": 0x70000000 # (shadow @0xf0000000)
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue