forked from M-Labs/artiq
gateware/targets: remove deprecated ofifo_depth parameter
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e2c1d4f3d5
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0824e0aeae
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@ -224,24 +224,22 @@ class NIST_CLOCK(_NIST_Ions):
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phy = spi.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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phy, ififo_depth=4))
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for i in range(3):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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phy, ififo_depth=128))
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phy = spi.SPIMaster(platform.request("sdcard_spi_33", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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phy, ififo_depth=4))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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@ -299,21 +297,19 @@ class NIST_QC2(_NIST_Ions):
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phy = spi.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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phy, ififo_depth=4))
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for i in range(4):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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phy, ififo_depth=128))
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for backplane_offset in range(2):
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phy = dds.AD9914(
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platform.request("dds", backplane_offset), 12, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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@ -101,12 +101,12 @@ class SMA_SPI(_NIST_Ions):
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phy = spi.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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phy, ififo_depth=4))
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phy = spi.SPIMaster(self.platform.request("sma_spi"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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phy, ififo_depth=128))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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@ -213,8 +213,7 @@ class Phaser(MiniSoC, AMPSoC):
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sysref_pads = platform.request("ad9154_sysref")
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phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32))
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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