diff --git a/artiq/coredevice/core.py b/artiq/coredevice/core.py
index c9d1bc1f4..ecc6c17ed 100644
--- a/artiq/coredevice/core.py
+++ b/artiq/coredevice/core.py
@@ -58,6 +58,12 @@ class Core:
         factor).
     :param comm_device: name of the device used for communications.
     """
+
+    kernel_constant_attributes = {
+        'core', 'ref_period', 'coarse_ref_period', 'ref_multiplier',
+        'external_clock',
+    }
+
     def __init__(self, dmgr, ref_period, external_clock=False,
                  ref_multiplier=8, comm_device="comm"):
         self.ref_period = ref_period
diff --git a/artiq/coredevice/dds.py b/artiq/coredevice/dds.py
index bc23f2cdf..0d7849571 100644
--- a/artiq/coredevice/dds.py
+++ b/artiq/coredevice/dds.py
@@ -29,6 +29,8 @@ def dds_batch_exit() -> TNone:
 
 
 class _BatchContextManager:
+    kernel_constant_attributes = {'core', 'core_dds'}
+
     def __init__(self, core_dds):
         self.core_dds = core_dds
         self.core = self.core_dds.core
@@ -50,6 +52,9 @@ class CoreDDS:
     :param sysclk: DDS system frequency. The DDS system clock must be a
         phase-locked multiple of the RTIO clock.
     """
+
+    kernel_constant_attributes = {'core', 'sysclk', 'batch'}
+
     def __init__(self, dmgr, sysclk, core_device="core"):
         self.core = dmgr.get(core_device)
         self.sysclk = sysclk
@@ -82,6 +87,11 @@ class _DDSGeneric:
     :param bus: name of the DDS bus device that this DDS is connected to.
     :param channel: channel number of the DDS device to control.
     """
+
+    kernel_constant_attributes = {
+        'core', 'core_dds', 'bus_channel', 'channel', 'pow_width'
+    }
+
     def __init__(self, dmgr, bus_channel, channel, core_dds_device="core_dds"):
         self.core_dds = dmgr.get(core_dds_device)
         self.core = self.core_dds.core