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correct documented siphaser VCO frequency [NFC]

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Chris Ballance 2018-06-04 12:28:44 +01:00 committed by Sébastien Bourdeauducq
parent 925b47b077
commit 07d4145a35
1 changed files with 1 additions and 1 deletions
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artiq/gateware/drtio/siphaser.py
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@ -14,7 +14,7 @@ class SiPhaser7Series(Module, AutoCSR):
self.phase_shift_done = CSRStatus(reset=1)
self.sample_result = CSRStatus()
# 125MHz/62.5MHz reference clock to 150MHz. VCO @ 625MHz.
# 125MHz/62.5MHz reference clock to 150MHz. VCO @ 750MHz.
# Used to provide a startup clock to the transceiver through the Si,
# we do not use the crystal reference so that the PFD (f3) frequency
# can be high.