forked from M-Labs/artiq
ad9910: add IO_UPDATE alignment and tuning
for #1143 Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -51,14 +51,19 @@ class AD9910:
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:param pll_cp: DDS PLL charge pump setting.
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:param pll_vco: DDS PLL VCO range selection.
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:param sync_delay_seed: SYNC_IN delay tuning starting value.
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To stabilize the SYNC_IN delay tuning, run :meth:`tune_sync_delay` once and
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set this to the delay tap number returned by :meth:`tune_sync_delay`.
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To stabilize the SYNC_IN delay tuning, run :meth:`tune_sync_delay` once
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and set this to the delay tap number returned (default: -1 to signal no
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synchronization and no tuning during :meth:`init`).
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:param io_update_delay: IO_UPDATE pulse alignment delay.
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To align IO_UPDATE to SYNC_CLK, run :meth:`tune_io_update_delay` and
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set this to the delay tap number returned.
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"""
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kernel_invariants = {"chip_select", "cpld", "core", "bus",
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"ftw_per_hz", "pll_n", "pll_cp", "pll_vco", "sync_delay_seed"}
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"ftw_per_hz", "pll_n", "io_update_delay"}
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=40, pll_cp=7, pll_vco=5, sync_delay_seed=8):
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pll_n=40, pll_cp=7, pll_vco=5, sync_delay_seed=-1,
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io_update_delay=0):
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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@ -81,6 +86,7 @@ class AD9910:
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assert 0 <= pll_cp <= 7
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self.pll_cp = pll_cp
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self.sync_delay_seed = sync_delay_seed
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self.io_update_delay = io_update_delay
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@kernel
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def write32(self, addr, data):
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@ -169,6 +175,8 @@ class AD9910:
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if lock & (1 << self.chip_select - 4):
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return
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raise ValueError("PLL lock timeout")
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if self.sync_delay_seed >= 0:
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self.tune_sync_delay(self.sync_delay_seed)
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@kernel
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def power_down(self, bits=0b1111):
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@ -191,6 +199,8 @@ class AD9910:
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:param asf: Amplitude scale factor: 14 bit unsigned.
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"""
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self.write64(_AD9910_REG_PR0, (asf << 16) | pow, ftw)
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# align IO_UPDATE to SYNC_CLK
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at_mu((now_mu() & ~0xf) | self.io_update_delay)
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self.cpld.io_update.pulse_mu(8)
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@portable(flags={"fast-math"})
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@ -290,30 +300,31 @@ class AD9910:
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self.cpld.io_update.pulse(1*us)
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@kernel
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def tune_sync_delay(self):
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def tune_sync_delay(self, sync_delay_seed):
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"""Find a stable SYNC_IN delay.
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This method first locates the smallest SYNC_IN validity window at
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minimum window size and then increases the window a bit to provide some
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slack and stability.
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It starts scanning delays around :attr:`sync_delay_seed` (see the
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It starts scanning delays around `sync_delay_seed` (see the
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device database arguments and :class:`AD9910`) at maximum validation
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window size and decreases the window size until a valid delay is found.
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:param sync_delay_seed: Start value for valid SYNC_IN delay search.
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:return: Tuple of optimal delay and window size.
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"""
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dt = 14 # 1/(f_SYSCLK*75ps) taps per SYSCLK period
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dt = 14 # 1/(f_SYSCLK*75ps) taps per SYSCLK period
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max_delay = dt # 14*75ps > 1ns
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max_window = dt//4 + 1 # 2*75ps*4 = 600ps high > 1ns/2
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min_window = dt//8 + 1 # 2*75ps hold, 2*75ps setup < 1ns/4
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min_window = max(0, max_window - 2) # 2*75ps hold, 2*75ps setup
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for window in range(max_window - min_window + 1):
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window = max_window - window
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for in_delay in range(max_delay):
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# alternate search direction around seed_delay
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if in_delay & 1:
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in_delay = -in_delay
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in_delay = self.sync_delay_seed + (in_delay >> 1)
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in_delay = sync_delay_seed + (in_delay >> 1)
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if in_delay < 0:
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in_delay = 0
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elif in_delay > 31:
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@ -371,3 +382,28 @@ class AD9910:
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self.write32(_AD9910_REG_CFR2, 0x01010000)
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self.cpld.io_update.pulse_mu(8)
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return ftw & 1
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@kernel
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def tune_io_update_delay(self):
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"""Find a stable IO_UPDATE delay alignment.
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Scan through increasing IO_UPDATE delays until a delay is found that
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lets IO_UPDATE be registered in the next SYNC_CLK cycle. Return a
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IO_UPDATE delay that is midway between two such SYNC_CLK transitions.
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This method assumes that the IO_UPDATE TTLOut device has one machine
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unit resolution (SERDES) and that the ratio between fine RTIO frequency
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(RTIO time machine units) and SYNC_CLK is 4.
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:return: Stable IO_UPDATE delay to be passed to the constructor
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:class:`AD9910` via the device database.
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"""
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period = 4 # f_RTIO/f_SYNC = 4
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max_delay = 8 # mu, 1 ns
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d0 = self.io_update_delay
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t0 = int32(self.measure_io_update_alignment(d0))
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for i in range(max_delay - 1):
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t = self.measure_io_update_alignment((d0 + i + 1) & (max_delay - 1))
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if t != t0:
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return (d0 + i + period//2) & (period - 1)
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raise ValueError("no IO_UPDATE-SYNC_CLK alignment edge found")
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@ -141,7 +141,7 @@ class CPLD:
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is not transferred between experiments.
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:param sync_div: SYNC_IN generator divider. The ratio between the coarse
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RTIO frequency and the SYNC_IN generator frequency (default: 2 if
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:param:`sync_device` was specified).
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`sync_device` was specified).
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:param core_device: Core device name
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"""
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kernel_invariants = {"refclk", "bus", "core", "io_update"}
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