From 051bafbfd973fe6938d7a6f59984c0b033d6caeb Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 11 Sep 2018 22:18:42 +0800 Subject: [PATCH] drtio: ensure 2 cycles between frames on the link This gives time for setting chan_sel before cmd on CRI. --- artiq/gateware/drtio/rt_packet_master.py | 4 ++++ artiq/gateware/drtio/rt_packet_repeater.py | 4 ++++ artiq/gateware/test/drtio/test_rt_packet_repeater.py | 3 +++ 3 files changed, 11 insertions(+) diff --git a/artiq/gateware/drtio/rt_packet_master.py b/artiq/gateware/drtio/rt_packet_master.py index 45ffe1278..42370a09d 100644 --- a/artiq/gateware/drtio/rt_packet_master.py +++ b/artiq/gateware/drtio/rt_packet_master.py @@ -208,6 +208,10 @@ class RTPacketMaster(Module): self.sync.rtio += If(tsc_value_load, tsc_value.eq(self.tsc_value)) tx_fsm.act("IDLE", + # Ensure 2 cycles between frames on the link. + NextState("READY") + ) + tx_fsm.act("READY", If(sr_buf_readable, If(sr_notwrite, Case(sr_address[0], { diff --git a/artiq/gateware/drtio/rt_packet_repeater.py b/artiq/gateware/drtio/rt_packet_repeater.py index 5ccd8dd70..1798b6da8 100644 --- a/artiq/gateware/drtio/rt_packet_repeater.py +++ b/artiq/gateware/drtio/rt_packet_repeater.py @@ -110,6 +110,10 @@ class RTPacketRepeater(Module): self.submodules += tx_fsm tx_fsm.act("IDLE", + # Ensure 2 cycles between frames on the link. + NextState("READY") + ) + tx_fsm.act("READY", If(self.set_time_stb, tsc_value_load.eq(1), NextState("SET_TIME") diff --git a/artiq/gateware/test/drtio/test_rt_packet_repeater.py b/artiq/gateware/test/drtio/test_rt_packet_repeater.py index d348a5efc..70f25adb0 100644 --- a/artiq/gateware/test/drtio/test_rt_packet_repeater.py +++ b/artiq/gateware/test/drtio/test_rt_packet_repeater.py @@ -27,6 +27,7 @@ class TestRepeater(unittest.TestCase): pt, pr, ts, dut = create_dut(nwords) def send(): + yield yield ts.eq(0x12345678) yield dut.set_time_stb.eq(1) while not (yield dut.set_time_ack): @@ -61,6 +62,7 @@ class TestRepeater(unittest.TestCase): pt, pr, ts, dut = create_dut(nwords) def send(): + yield for channel, timestamp, address, data in test_writes: yield dut.cri.chan_sel.eq(channel) yield dut.cri.timestamp.eq(timestamp) @@ -96,6 +98,7 @@ class TestRepeater(unittest.TestCase): def send_requests(): for i in range(10): + yield yield dut.cri.chan_sel.eq(i << 16) yield dut.cri.cmd.eq(cri.commands["get_buffer_space"]) yield