forked from M-Labs/artiq
examples/simple_simulation: do not provide unneeded core device
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@ -18,13 +18,12 @@ if __name__ == "__main__":
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from artiq.sim import devices as sd
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from artiq.sim import time
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coredev = sd.Core()
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exp = SimpleSimulation(
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core=coredev,
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a=sd.WaveOutput(core=coredev, name="a"),
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b=sd.WaveOutput(core=coredev, name="b"),
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c=sd.WaveOutput(core=coredev, name="c"),
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d=sd.WaveOutput(core=coredev, name="d"),
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core=sd.Core(),
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a=sd.WaveOutput(name="a"),
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b=sd.WaveOutput(name="b"),
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c=sd.WaveOutput(name="c"),
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d=sd.WaveOutput(name="d"),
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)
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exp.run()
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print(time.manager.format_timeline())
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