srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

suservo: sampler channels are reversed

This commit is contained in:
Robert Jördens 2018-05-11 12:46:12 +00:00
parent 7e299563df
commit 04240cdc08
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/suservo/servo.py
View File

@ -11,7 +11,7 @@ class Servo(Module):
self.submodules.iir = IIR(iir_p) self.submodules.iir = IIR(iir_p)
self.submodules.dds = DDS(dds_pads, dds_p) self.submodules.dds = DDS(dds_pads, dds_p)
for i, j, k, l in zip(self.adc.data, self.iir.adc, for i, j, k, l in zip(reversed(self.adc.data), self.iir.adc,
self.iir.dds, self.dds.profile): self.iir.dds, self.dds.profile):
self.comb += j.eq(i), l.eq(k) self.comb += j.eq(i), l.eq(k)

2
artiq/gateware/test/suservo/test_servo.py
View File

@ -28,7 +28,7 @@ class ServoSim(servo.Servo):
adc = 1 adc = 1
x0 = 0x0141 x0 = 0x0141
yield self.adc_tb.data[adc].eq(x0) yield self.adc_tb.data[-adc-1].eq(x0)
channel = 3 channel = 3
yield self.iir.adc[channel].eq(adc) yield self.iir.adc[channel].eq(adc)
yield self.iir.ctrl[channel].en_iir.eq(1) yield self.iir.ctrl[channel].en_iir.eq(1)