forked from M-Labs/artiq
drtio: RX clock alignment and ready
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@ -9,6 +9,11 @@ class DRTIOSatellite(Module):
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def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders)
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self.comb += [
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transceiver.rx_reset.eq(self.link_layer.rx_reset),
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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]
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link_layer_sync = SimpleNamespace(
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tx_aux_frame=self.link_layer.tx.aux_frame,
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tx_aux_data=self.link_layer.tx_aux_data,
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@ -24,6 +29,7 @@ class DRTIOSatellite(Module):
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)
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self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
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rt_packets.RTPacketSatellite(link_layer_sync))
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self.submodules.iot = ClockDomainsRenamer("rtio")(
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iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width))
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@ -164,7 +164,15 @@ class GTX_1000BASE_BX10(Module):
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self.decoders[0].input.eq(rxdata[:10]),
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self.decoders[1].input.eq(rxdata[10:])
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]
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# TODO: clock aligner, reset/ready
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clock_aligner = BruteforceClockAligner(0b0011111000, 62.5e6)
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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rx_init.restart.eq(clock_aligner.restart),
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clock_aligner.reset.eq(self.rx_reset),
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self.rx_ready.eq(clock_aligner.ready)
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]
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class RXSynchronizer(Module):
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@ -131,20 +131,25 @@ class GTXInit(Module):
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# Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
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# transceiver "feature".
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class BruteforceClockAligner(Module):
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def __init__(self, comma, sys_clk_freq, check_period=6e-3):
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def __init__(self, comma, rtio_clk_freq, check_period=6e-3, ready_time=50e-3):
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self.rxdata = Signal(20)
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self.restart = Signal()
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check_max_val = ceil(check_period*sys_clk_freq)
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self.reset = Signal()
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self.ready = Signal()
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check_max_val = ceil(check_period*rtio_clk_freq)
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check_counter = Signal(max=check_max_val+1)
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check = Signal()
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self.sync += [
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self.sync.rtio += [
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check.eq(0),
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If(check_counter == 0,
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check.eq(1),
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check_counter.eq(check_max_val)
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).Else(
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check_counter.eq(check_counter-1)
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If(~self.ready,
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If(check_counter == 0,
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check.eq(1),
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check_counter.eq(check_max_val)
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).Else(
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check_counter.eq(check_counter-1)
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)
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)
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]
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@ -154,7 +159,7 @@ class BruteforceClockAligner(Module):
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self.specials += MultiReg(comma_seen_rxclk, comma_seen)
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comma_seen_reset = PulseSynchronizer("sys", "rx")
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self.submodules += comma_seen_reset
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self.sync.rx += \
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self.sync.rtio_rx += \
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If(comma_seen_reset.o,
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comma_seen_rxclk.eq(0)
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).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
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@ -166,3 +171,18 @@ class BruteforceClockAligner(Module):
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If(~comma_seen, self.restart.eq(1)),
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comma_seen_reset.i.eq(1)
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)
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ready_counts = ceil(ready_time/check_period)
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assert ready_counts > 1
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ready_counter = Signal(max=ready_counts+1, reset=ready_counts)
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self.sync.rtio += [
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If(check,
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If(comma_seen,
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If(ready_counter != 0, ready_counter.eq(ready_counter-1))
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).Else(
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ready_counter.eq(ready_counts)
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)
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),
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If(self.reset, ready_counter.eq(ready_counts))
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]
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self.comb += self.ready.eq(ready_counter == 0)
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