forked from M-Labs/artiq
phaser: dma/drtio changes
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c63fa46430
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03d13d3811
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@ -151,10 +151,11 @@ class AD9154(Module, AutoCSR):
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class Phaser(MiniSoC, AMPSoC):
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mem_map = {
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"timer_kernel": 0x10000000, # (shadow @0x90000000)
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"i2c": 0x30000000, # (shadow @0xb0000000)
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"mailbox": 0x70000000, # (shadow @0xf0000000)
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"timer_kernel": 0x10000000,
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"rtio": 0x20000000,
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# "rtio_dma": 0x30000000,
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"i2c": 0x30000000,
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"mailbox": 0x70000000,
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"ad9154": 0x50000000,
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}
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mem_map.update(MiniSoC.mem_map)
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@ -219,6 +220,7 @@ class Phaser(MiniSoC, AMPSoC):
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for sawg in self.ad9154.sawgs
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for phy in sawg.phys)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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@ -227,20 +229,25 @@ class Phaser(MiniSoC, AMPSoC):
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self.config["DDS_CHANNELS_PER_BUS"] = 1
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self.config["DDS_AD9914"] = None
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self.config["DDS_ONEHOT_SEL"] = None
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self.config["DDS_RTIO_CLK_RATIO"] = 8
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self.submodules.rtio_crg = _PhaserCRG(
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platform, self.ad9154.jesd.cd_jesd.clk)
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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# self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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self.register_kernel_cpu_csrdevice("rtio")
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# self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri], # , self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(
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self.rtio, self.get_native_sdram_if())
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self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.rtio_crg.cd_rtio.clk)
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platform.add_false_path_constraints(
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