From 03b803e7642fd295259f3c4a5312e0b496057599 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:57:30 +0800 Subject: [PATCH] firmware: adjust csr separation --- artiq/firmware/ksupport/rtio.rs | 6 ++++-- artiq/firmware/libboard_artiq/rpc_queue.rs | 6 +++--- artiq/firmware/libboard_misoc/sdram.rs | 15 +++++++++------ 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/artiq/firmware/ksupport/rtio.rs b/artiq/firmware/ksupport/rtio.rs index 8736e33f5..d9f568f75 100644 --- a/artiq/firmware/ksupport/rtio.rs +++ b/artiq/firmware/ksupport/rtio.rs @@ -23,6 +23,8 @@ mod imp { pub const RTIO_I_STATUS_WAIT_STATUS: u8 = 4; pub const RTIO_I_STATUS_DESTINATION_UNREACHABLE: u8 = 8; + const OFFSET_MULTIPLE: isize = (csr::CONFIG_DATA_WIDTH_BYTES / 4) as isize; + pub extern fn init() { send(&RtioInitRequest); } @@ -47,14 +49,14 @@ mod imp { #[inline(always)] pub unsafe fn rtio_o_data_write(offset: usize, data: u32) { write_volatile( - csr::rtio::O_DATA_ADDR.offset((csr::rtio::O_DATA_SIZE - 1 - offset) as isize), + csr::rtio::O_DATA_ADDR.offset(OFFSET_MULTIPLE*(csr::rtio::O_DATA_SIZE - 1 - offset) as isize), data); } #[inline(always)] pub unsafe fn rtio_i_data_read(offset: usize) -> u32 { read_volatile( - csr::rtio::I_DATA_ADDR.offset((csr::rtio::I_DATA_SIZE - 1 - offset) as isize)) + csr::rtio::I_DATA_ADDR.offset(OFFSET_MULTIPLE*(csr::rtio::I_DATA_SIZE - 1 - offset) as isize)) } #[inline(never)] diff --git a/artiq/firmware/libboard_artiq/rpc_queue.rs b/artiq/firmware/libboard_artiq/rpc_queue.rs index 0e2049c81..877ed8c89 100644 --- a/artiq/firmware/libboard_artiq/rpc_queue.rs +++ b/artiq/firmware/libboard_artiq/rpc_queue.rs @@ -1,9 +1,9 @@ use core::ptr::{read_volatile, write_volatile}; use core::slice; -use board_misoc::{mem, cache}; +use board_misoc::{mem, cache, csr::CONFIG_DATA_WIDTH_BYTES}; -const SEND_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 4) as *mut usize; -const RECV_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 8) as *mut usize; +const SEND_MAILBOX: *mut usize = (mem::MAILBOX_BASE + CONFIG_DATA_WIDTH_BYTES as usize) as *mut usize; +const RECV_MAILBOX: *mut usize = (mem::MAILBOX_BASE + (CONFIG_DATA_WIDTH_BYTES * 2) as usize) as *mut usize; const QUEUE_BEGIN: usize = 0x44000000; const QUEUE_END: usize = 0x44ffff80; diff --git a/artiq/firmware/libboard_misoc/sdram.rs b/artiq/firmware/libboard_misoc/sdram.rs index 61951e725..b3e112eb0 100644 --- a/artiq/firmware/libboard_misoc/sdram.rs +++ b/artiq/firmware/libboard_misoc/sdram.rs @@ -2,6 +2,7 @@ mod ddr { use core::{ptr, fmt}; use csr::{dfii, ddrphy}; + use csr::CONFIG_DATA_WIDTH_BYTES; use sdram_phy::{self, spin_cycles}; use sdram_phy::{DFII_COMMAND_CS, DFII_COMMAND_WE, DFII_COMMAND_CAS, DFII_COMMAND_RAS, DFII_COMMAND_WRDATA, DFII_COMMAND_RDDATA}; @@ -14,6 +15,8 @@ mod ddr { const DQS_SIGNAL_COUNT: usize = DFII_PIX_DATA_SIZE / 2; + const CSR_SEPARATION: isize = CONFIG_DATA_WIDTH_BYTES as isize / 4; + macro_rules! log { ($logger:expr, $( $arg:expr ),+) => ( if let &mut Some(ref mut f) = $logger { @@ -46,7 +49,7 @@ mod ddr { for n in 0..DQS_SIGNAL_COUNT { let dq_addr = dfii::PI0_RDDATA_ADDR - .offset((DQS_SIGNAL_COUNT - 1 - n) as isize); + .offset(CSR_SEPARATION * (DQS_SIGNAL_COUNT - 1 - n) as isize); log!(logger, "Module {}:\n", DQS_SIGNAL_COUNT - 1 - n); @@ -100,7 +103,7 @@ mod ddr { let mut failed = false; for n in 0..DQS_SIGNAL_COUNT { let dq_addr = dfii::PI0_RDDATA_ADDR - .offset((DQS_SIGNAL_COUNT - 1 - n) as isize); + .offset(CSR_SEPARATION * (DQS_SIGNAL_COUNT - 1 - n) as isize); delay[n] = 0; high_skew[n] = false; @@ -223,7 +226,7 @@ mod ddr { // Write test pattern for p in 0..DFII_NPHASES { for offset in 0..DFII_PIX_DATA_SIZE { - let addr = DFII_PIX_WRDATA_ADDR[p].offset(offset as isize); + let addr = DFII_PIX_WRDATA_ADDR[p].offset(CSR_SEPARATION * offset as isize); let data = prs[DFII_PIX_DATA_SIZE * p + offset]; ptr::write_volatile(addr, data as u32); } @@ -258,7 +261,7 @@ mod ddr { for p in 0..DFII_NPHASES { for &offset in [n, n + DQS_SIGNAL_COUNT].iter() { - let addr = DFII_PIX_RDDATA_ADDR[p].offset(offset as isize); + let addr = DFII_PIX_RDDATA_ADDR[p].offset(CSR_SEPARATION * offset as isize); let data = prs[DFII_PIX_DATA_SIZE * p + offset]; if ptr::read_volatile(addr) as u8 != data { working = false; @@ -306,7 +309,7 @@ mod ddr { // Write test pattern for p in 0..DFII_NPHASES { for offset in 0..DFII_PIX_DATA_SIZE { - let addr = DFII_PIX_WRDATA_ADDR[p].offset(offset as isize); + let addr = DFII_PIX_WRDATA_ADDR[p].offset(CSR_SEPARATION * offset as isize); let data = prs[DFII_PIX_DATA_SIZE * p + offset]; ptr::write_volatile(addr, data as u32); } @@ -349,7 +352,7 @@ mod ddr { for p in 0..DFII_NPHASES { for &offset in [n, n + DQS_SIGNAL_COUNT].iter() { - let addr = DFII_PIX_RDDATA_ADDR[p].offset(offset as isize); + let addr = DFII_PIX_RDDATA_ADDR[p].offset(CSR_SEPARATION * offset as isize); let data = prs[DFII_PIX_DATA_SIZE * p + offset]; if ptr::read_volatile(addr) as u8 != data { valid = false;