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sayma_amc: sma -> mcx

This commit is contained in:
Sebastien Bourdeauducq 2019-10-07 20:31:35 +08:00
parent ebd5d890f1
commit 03007b896e
1 changed files with 18 additions and 18 deletions
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36
artiq/gateware/targets/sayma_amc.py
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@ -246,14 +246,14 @@ class Satellite(SatelliteBase):
phy = ttl_simple.Output(platform.request("user_led", i)) phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0) mcx_io = platform.request("mcx_io", 0)
self.comb += sma_io.direction.eq(1) self.comb += mcx_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level) phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1) mcx_io = platform.request("mcx_io", 1)
self.comb += sma_io.direction.eq(0) self.comb += mcx_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
@ -298,14 +298,14 @@ class SimpleSatellite(SatelliteBase):
phy = ttl_simple.Output(platform.request("user_led", i)) phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0) mcx_io = platform.request("mcx_io", 0)
self.comb += sma_io.direction.eq(1) self.comb += mcx_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level) phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1) mcx_io = platform.request("mcx_io", 1)
self.comb += sma_io.direction.eq(0) self.comb += mcx_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
@ -416,14 +416,14 @@ class Master(MiniSoC, AMPSoC):
phy = ttl_simple.Output(platform.request("user_led", i)) phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0) mcx_io = platform.request("mcx_io", 0)
self.comb += sma_io.direction.eq(1) self.comb += mcx_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level) phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1) mcx_io = platform.request("mcx_io", 1)
self.comb += sma_io.direction.eq(0) self.comb += mcx_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))