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soc: add_cpu_csr_region -> add_csr_region

This commit is contained in:
Joe Britton 2015-02-27 15:02:28 -07:00
parent f307897bec
commit 0127de9bb5
2 changed files with 2 additions and 2 deletions
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2
soc/targets/artiq_kc705.py
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@ -103,7 +103,7 @@ class ARTIQSoC(BaseSoC):
rtio_csrs = self.rtio.get_csrs() rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus) self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs) self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
dds_pads = platform.request("dds") dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads) self.submodules.dds = ad9858.AD9858(dds_pads)

2
soc/targets/artiq_ppro.py
View File

@ -122,7 +122,7 @@ class ARTIQMiniSoC(BaseSoC):
rtio_csrs = self.rtio.get_csrs() rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus) self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs) self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
if with_test_gen: if with_test_gen:
self.submodules.test_gen = _TestGen(platform.request("ttl", 8)) self.submodules.test_gen = _TestGen(platform.request("ttl", 8))