forked from M-Labs/artiq
1
0
Fork 0

rename 'RTM identifier' to 'RTM magic number'

Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
This commit is contained in:
Sebastien Bourdeauducq 2018-02-13 19:58:51 +08:00
parent 96b948f57f
commit 00f42f912b
2 changed files with 10 additions and 10 deletions

View File

@ -38,12 +38,12 @@ pub fn wait_init() {
} }
info!("done."); info!("done.");
// Try reading the identifier register on the other side of the bridge. // Try reading the magic number register on the other side of the bridge.
let rtm_identifier = unsafe { let rtm_magic = unsafe {
csr::rtm_identifier::identifier_read() csr::rtm_magic::magic_read()
}; };
if rtm_identifier != 0x5352544d { if rtm_magic != 0x5352544d {
error!("incorrect RTM identifier: 0x{:08x}", rtm_identifier); error!("incorrect RTM magic number: 0x{:08x}", rtm_magic);
// proceed anyway // proceed anyway
} }

View File

@ -61,10 +61,10 @@ class CRG(Module):
self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
class RTMIdentifier(Module, AutoCSR): class RTMMagic(Module, AutoCSR):
def __init__(self): def __init__(self):
self.identifier = CSRStatus(32) self.magic = CSRStatus(32)
self.comb += self.identifier.status.eq(0x5352544d) # "SRTM" self.comb += self.magic.status.eq(0x5352544d) # "SRTM"
CSR_RANGE_SIZE = 0x800 CSR_RANGE_SIZE = 0x800
@ -83,8 +83,8 @@ class SaymaRTM(Module):
self.submodules.crg = CRG(platform) self.submodules.crg = CRG(platform)
clk_freq = 125e6 clk_freq = 125e6
self.submodules.rtm_identifier = RTMIdentifier() self.submodules.rtm_magic = RTMMagic()
csr_devices.append("rtm_identifier") csr_devices.append("rtm_magic")
# clock mux: 100MHz ext SMA clock to HMC830 input # clock mux: 100MHz ext SMA clock to HMC830 input
self.submodules.clock_mux = gpio.GPIOOut(Cat( self.submodules.clock_mux = gpio.GPIOOut(Cat(