forked from M-Labs/artiq
Move mu_to_seconds, seconds_to_mu to Core.
This commit is contained in:
parent
06ea76336d
commit
009d396740
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@ -203,12 +203,6 @@ def fn_delay_mu():
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def fn_at_mu():
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return types.TBuiltinFunction("at_mu")
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def fn_mu_to_seconds():
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return types.TBuiltinFunction("mu_to_seconds")
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def fn_seconds_to_mu():
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return types.TBuiltinFunction("seconds_to_mu")
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def fn_rtio_log():
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return types.TBuiltinFunction("rtio_log")
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@ -44,8 +44,6 @@ def globals():
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"now_mu": builtins.fn_now_mu(),
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"delay_mu": builtins.fn_delay_mu(),
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"at_mu": builtins.fn_at_mu(),
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"mu_to_seconds": builtins.fn_mu_to_seconds(),
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"seconds_to_mu": builtins.fn_seconds_to_mu(),
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# ARTIQ utility functions
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"rtio_log": builtins.fn_rtio_log(),
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@ -1731,20 +1731,6 @@ class ARTIQIRGenerator(algorithm.Visitor):
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or types.is_builtin(typ, "at_mu"):
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return self.append(ir.Builtin(typ.name,
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[self.visit(arg) for arg in node.args], node.type))
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elif types.is_builtin(typ, "mu_to_seconds"):
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if len(node.args) == 1 and len(node.keywords) == 0:
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arg = self.visit(node.args[0])
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arg_float = self.append(ir.Coerce(arg, builtins.TFloat()))
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return self.append(ir.Arith(ast.Mult(loc=None), arg_float, self.ref_period))
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else:
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assert False
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elif types.is_builtin(typ, "seconds_to_mu"):
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if len(node.args) == 1 and len(node.keywords) == 0:
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arg = self.visit(node.args[0])
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arg_mu = self.append(ir.Arith(ast.Div(loc=None), arg, self.ref_period))
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return self.append(ir.Coerce(arg_mu, builtins.TInt64()))
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else:
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assert False
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elif types.is_exn_constructor(typ):
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return self.alloc_exn(node.type, *[self.visit(arg_node) for arg_node in node.args])
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elif types.is_constructor(typ):
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@ -899,12 +899,6 @@ class Inferencer(algorithm.Visitor):
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elif types.is_builtin(typ, "at_mu"):
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simple_form("at_mu(time_mu:numpy.int64) -> None",
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[builtins.TInt64()])
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elif types.is_builtin(typ, "mu_to_seconds"):
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simple_form("mu_to_seconds(time_mu:numpy.int64) -> float",
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[builtins.TInt64()], builtins.TFloat())
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elif types.is_builtin(typ, "seconds_to_mu"):
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simple_form("seconds_to_mu(time:float) -> numpy.int64",
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[builtins.TFloat()], builtins.TInt64())
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elif types.is_builtin(typ, "watchdog"):
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simple_form("watchdog(time:float) -> [builtin context manager]",
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[builtins.TFloat()], builtins.TNone())
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@ -1,5 +1,4 @@
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from artiq.language.core import (kernel, portable, delay_mu, delay,
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seconds_to_mu)
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from artiq.language.core import (kernel, portable, delay_mu, delay)
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from artiq.language.units import ns, us
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from artiq.coredevice import spi
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@ -166,10 +165,10 @@ class AD5360:
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self.bus.write_period_mu +
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self.bus.ref_period_mu) -
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3*self.bus.ref_period_mu -
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seconds_to_mu(1.5*us))
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self.core.seconds_to_mu(1.5*us))
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for i in range(len(values)):
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self.write_channel(i, values[i], op)
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delay_mu(3*self.bus.ref_period_mu + # latency alignment ttl to spi
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seconds_to_mu(1.5*us)) # t10 max busy low for one channel
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self.core.seconds_to_mu(1.5*us)) # t10 max busy low for one channel
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self.load()
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delay_mu(-2*self.bus.ref_period_mu) # load(), t13
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@ -1,4 +1,5 @@
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import os, sys
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import numpy
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from pythonparser import diagnostic
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@ -124,6 +125,23 @@ class Core:
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return result
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@portable
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def seconds_to_mu(self, seconds):
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"""Converts seconds to the corresponding number of machine units
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(RTIO cycles).
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:param seconds: time (in seconds) to convert.
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"""
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return numpy.int64(seconds//self.ref_period)
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@portable
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def mu_to_seconds(self, mu):
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"""Converts machine units (RTIO cycles) to seconds.
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:param mu: cycle count to convert.
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"""
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return mu*self.ref_period
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@kernel
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def get_rtio_counter_mu(self):
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return rtio_get_counter()
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@ -1,7 +1,6 @@
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import numpy
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from artiq.language.core import (kernel, portable, seconds_to_mu, now_mu,
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delay_mu, mu_to_seconds)
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from artiq.language.core import (kernel, portable, now_mu, delay_mu)
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from artiq.language.units import MHz
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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@ -59,8 +58,7 @@ class SPIMaster:
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"""
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.ref_period_mu = seconds_to_mu(self.core.coarse_ref_period,
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self.core)
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self.ref_period_mu = self.core.seconds_to_mu(self.core.coarse_ref_period)
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self.channel = channel
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self.write_period_mu = numpy.int64(0)
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self.read_period_mu = numpy.int64(0)
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@ -68,7 +66,7 @@ class SPIMaster:
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@portable
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def frequency_to_div(self, f):
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return int(1/(f*mu_to_seconds(self.ref_period_mu))) + 1
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return int(1/(f*self.core.mu_to_seconds(self.ref_period_mu))) + 1
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@kernel
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def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
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@ -94,7 +94,7 @@ class _Frame:
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def _arm(self):
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self.segment_delays = [
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seconds_to_mu(s.duration*delay_margin_factor, self.core)
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self.core.seconds_to_mu(s.duration*delay_margin_factor)
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for s in self.segments]
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def _invalidate(self):
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@ -125,7 +125,7 @@ class _Frame:
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raise ArmError()
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call_t = now_mu()
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trigger_start_t = call_t - seconds_to_mu(trigger_duration/2)
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trigger_start_t = call_t - self.core.seconds_to_mu(trigger_duration/2)
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if self.pdq.current_frame >= 0:
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# PDQ is in the middle of a frame. Check it is us.
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@ -136,7 +136,7 @@ class _Frame:
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# to play our first segment.
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self.pdq.current_frame = self.frame_number
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self.pdq.next_segment = 0
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at_mu(trigger_start_t - seconds_to_mu(frame_setup))
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at_mu(trigger_start_t - self.core.seconds_to_mu(frame_setup))
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self.pdq.frame0.set_o(bool(self.frame_number & 1))
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self.pdq.frame1.set_o(bool((self.frame_number & 2) >> 1))
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self.pdq.frame2.set_o(bool((self.frame_number & 4) >> 2))
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@ -5,10 +5,10 @@ class IdleKernel(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("led")
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@kernel
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def run(self):
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start_time = now_mu() + seconds_to_mu(500*ms)
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start_time = now_mu() + self.core.seconds_to_mu(500*ms)
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while self.core.get_rtio_counter_mu() < start_time:
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pass
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self.core.reset()
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@ -42,7 +42,7 @@ class TDR(EnvExperiment):
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pulse = 1e-6 # pulse length, larger than rtt
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self.t = [0 for i in range(2)]
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try:
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self.many(n, seconds_to_mu(pulse, self.core))
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self.many(n, self.core.seconds_to_mu(pulse))
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except PulseNotReceivedError:
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print("to few edges: cable too long or wiring bad")
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else:
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@ -15,7 +15,6 @@ __all__ = ["kernel", "portable", "rpc", "syscall", "host_only",
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kernel_globals = (
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"sequential", "parallel", "interleave",
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"delay_mu", "now_mu", "at_mu", "delay",
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"seconds_to_mu", "mu_to_seconds",
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"watchdog"
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)
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__all__.extend(kernel_globals)
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@ -213,31 +212,6 @@ def delay(duration):
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_time_manager.take_time(duration)
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def seconds_to_mu(seconds, core=None):
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"""Converts seconds to the corresponding number of machine units
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(RTIO cycles).
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:param seconds: time (in seconds) to convert.
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:param core: core device for which to perform the conversion. Specify only
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when running in the interpreter (not in kernel).
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"""
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if core is None:
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raise ValueError("Core device must be specified for time conversion")
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return numpy.int64(seconds//core.ref_period)
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def mu_to_seconds(mu, core=None):
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"""Converts machine units (RTIO cycles) to seconds.
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:param mu: cycle count to convert.
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:param core: core device for which to perform the conversion. Specify only
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when running in the interpreter (not in kernel).
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"""
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if core is None:
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raise ValueError("Core device must be specified for time conversion")
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return mu*core.ref_period
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class _DummyWatchdog:
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def __init__(self, timeout):
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pass
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@ -1,4 +1,5 @@
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from random import Random
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import numpy
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from artiq.language.core import delay, at_mu, kernel
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from artiq.sim import time
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@ -18,6 +19,12 @@ class Core:
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time.manager.timeline.clear()
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return r
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def seconds_to_mu(self, seconds):
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return numpy.int64(seconds//self.ref_period)
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def mu_to_seconds(self, mu):
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return mu*self.ref_period
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class Input:
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def __init__(self, dmgr, name):
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@ -83,7 +83,7 @@ class _PulseLogger(EnvExperiment):
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if not hasattr(self.parent_test, "first_timestamp"):
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self.parent_test.first_timestamp = t
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origin = self.parent_test.first_timestamp
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t_usec = round(mu_to_seconds(t-origin, self.core)*1000000)
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t_usec = round(self.core.mu_to_seconds(t-origin)*1000000)
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self.parent_test.output_list.append((self.name, t_usec, l, f))
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def on(self, t, f):
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@ -38,7 +38,7 @@ class RTT(EnvExperiment):
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t1 = self.ttl_inout.timestamp_mu()
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if t1 < 0:
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raise PulseNotReceived()
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self.set_dataset("rtt", mu_to_seconds(t1 - t0))
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self.set_dataset("rtt", self.core.mu_to_seconds(t1 - t0))
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class Loopback(EnvExperiment):
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@ -62,7 +62,7 @@ class Loopback(EnvExperiment):
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t1 = self.loop_in.timestamp_mu()
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if t1 < 0:
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raise PulseNotReceived()
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self.set_dataset("rtt", mu_to_seconds(t1 - t0))
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self.set_dataset("rtt", self.core.mu_to_seconds(t1 - t0))
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class ClockGeneratorLoopback(EnvExperiment):
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@ -93,7 +93,7 @@ class PulseRate(EnvExperiment):
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@kernel
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def run(self):
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self.core.reset()
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dt = seconds_to_mu(300*ns)
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dt = self.core.seconds_to_mu(300*ns)
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while True:
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for i in range(10000):
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try:
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@ -104,7 +104,7 @@ class PulseRate(EnvExperiment):
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self.core.break_realtime()
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break
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else:
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self.set_dataset("pulse_rate", mu_to_seconds(dt))
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self.set_dataset("pulse_rate", self.core.mu_to_seconds(dt))
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return
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@ -118,7 +118,7 @@ class PulseRateDDS(EnvExperiment):
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@kernel
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def run(self):
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self.core.reset()
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dt = seconds_to_mu(5*us)
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dt = self.core.seconds_to_mu(5*us)
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while True:
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delay(10*ms)
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for i in range(1250):
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@ -132,7 +132,7 @@ class PulseRateDDS(EnvExperiment):
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self.core.break_realtime()
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break
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else:
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self.set_dataset("pulse_rate", mu_to_seconds(dt//2))
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self.set_dataset("pulse_rate", self.core.mu_to_seconds(dt//2))
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return
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@ -403,7 +403,7 @@ class CoredeviceTest(ExperimentCase):
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self.execute(TimeKeepsRunning)
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t2 = self.dataset_mgr.get("time_at_start")
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dead_time = mu_to_seconds(t2 - t1, self.device_mgr.get("core"))
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dead_time = self.core.mu_to_seconds(t2 - t1, self.device_mgr.get("core"))
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print(dead_time)
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self.assertGreater(dead_time, 1*ms)
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self.assertLess(dead_time, 2500*ms)
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@ -434,7 +434,7 @@ class RPCTiming(EnvExperiment):
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t1 = self.core.get_rtio_counter_mu()
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self.nop()
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t2 = self.core.get_rtio_counter_mu()
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self.ts[i] = mu_to_seconds(t2 - t1)
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self.ts[i] = self.core.mu_to_seconds(t2 - t1)
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def run(self):
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self.ts = [0. for _ in range(self.repeats)]
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@ -1,5 +0,0 @@
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# RUN: %python -m artiq.compiler.testbench.jit %s
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# REQUIRES: time
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assert seconds_to_mu(2.0) == 2000000
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assert mu_to_seconds(1500000) == 1.5
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@ -151,7 +151,7 @@ In the synthetic example above, the compiler will be able to detect that the res
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@kernel
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def loop(self):
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precomputed_delay_mu = seconds_to_mu(self.worker.interval / 5.0)
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precomputed_delay_mu = self.core.seconds_to_mu(self.worker.interval / 5.0)
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for _ in range(100):
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delay_mu(precomputed_delay_mu)
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self.worker.work()
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@ -36,7 +36,7 @@ The wall clock keeps running across experiments.
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Absolute timestamps can be large numbers.
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They are represented internally as 64-bit integers with a resolution of typically a nanosecond and a range of hundreds of years.
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Conversions between such a large integer number and a floating point representation can cause loss of precision through cancellation.
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When computing the difference of absolute timestamps, use ``mu_to_seconds(t2-t1)``, not ``mu_to_seconds(t2)-mu_to_seconds(t1)`` (see :meth:`artiq.language.core.mu_to_seconds`).
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When computing the difference of absolute timestamps, use ``self.core.mu_to_seconds(t2-t1)``, not ``self.core.mu_to_seconds(t2)-self.core.mu_to_seconds(t1)`` (see :meth:`artiq.coredevice.Core.mu_to_seconds`).
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When accumulating time, do it in machine units and not in SI units, so that rounding errors do not accumulate.
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The following basic example shows how to place output events on the timeline.
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