forked from M-Labs/artiq
build_soc: rename identifier_str to gateware_identifier_str
This commit is contained in:
parent
4398a2d5fa
commit
002a71dd8d
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@ -44,14 +44,15 @@ class ReprogrammableIdentifier(Module, AutoCSR):
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p_INIT=sum(1 << j if c & (1 << i) else 0 for j, c in enumerate(contents)))
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p_INIT=sum(1 << j if c & (1 << i) else 0 for j, c in enumerate(contents)))
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def add_identifier(soc, *args, identifier_str=None, **kwargs):
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def add_identifier(soc, *args, gateware_identifier_str=None, **kwargs):
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if hasattr(soc, "identifier"):
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if hasattr(soc, "identifier"):
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raise ValueError
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raise ValueError
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software_identifier_str = get_identifier_string(soc, *args, **kwargs)
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if gateware_identifier_str is None:
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gateware_identifier_str = identifier_str or software_identifier_str
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# not overridden with --identifier-str
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raise ValueError("gateware_identifier_str not overridden")
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soc.submodules.identifier = ReprogrammableIdentifier(gateware_identifier_str)
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identifier_str = get_identifier_string(soc, *args, **kwargs)
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soc.config["IDENTIFIER_STR"] = software_identifier_str
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soc.submodules.identifier = ReprogrammableIdentifier(gateware_identifier_str or identifier_str)
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soc.config["IDENTIFIER_STR"] = identifier_str
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def build_artiq_soc(soc, argdict):
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def build_artiq_soc(soc, argdict):
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@ -99,7 +99,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
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}
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}
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mem_map.update(MiniSoC.mem_map)
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, identifier_str=None, **kwargs):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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@ -109,7 +109,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
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ethmac_ntxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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add_identifier(self, identifier_str=identifier_str)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if self.platform.hw_rev == "v2.0":
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if self.platform.hw_rev == "v2.0":
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.submodules.error_led = gpio.GPIOOut(Cat(
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@ -280,7 +280,7 @@ class MasterBase(MiniSoC, AMPSoC):
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}
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}
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mem_map.update(MiniSoC.mem_map)
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, identifier_str=None, **kwargs):
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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@ -290,7 +290,7 @@ class MasterBase(MiniSoC, AMPSoC):
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ethmac_ntxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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add_identifier(self, identifier_str=identifier_str)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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platform = self.platform
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platform = self.platform
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@ -453,13 +453,13 @@ class SatelliteBase(BaseSoC):
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}
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}
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mem_map.update(BaseSoC.mem_map)
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, identifier_str=None, **kwargs):
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs):
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BaseSoC.__init__(self,
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BaseSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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l2_size=128*1024,
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**kwargs)
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**kwargs)
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add_identifier(self, identifier_str=identifier_str)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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platform = self.platform
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platform = self.platform
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@ -674,14 +674,14 @@ def main():
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help="variant: {} (default: %(default)s)".format(
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help="variant: {} (default: %(default)s)".format(
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"/".join(sorted(VARIANTS.keys()))))
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"/".join(sorted(VARIANTS.keys()))))
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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parser.add_argument("--identifier-str", default=None,
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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help="Override ROM identifier")
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args = parser.parse_args()
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args = parser.parse_args()
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argdict = dict()
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argdict = dict()
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if args.with_wrpll:
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if args.with_wrpll:
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argdict["with_wrpll"] = True
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argdict["with_wrpll"] = True
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argdict["identifier_str"] = args.identifier_str
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argdict["gateware_identifier_str"] = args.gateware_identifier_str
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variant = args.variant.lower()
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variant = args.variant.lower()
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try:
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try:
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@ -252,7 +252,7 @@ def main():
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parser.set_defaults(output_dir="artiq_kasli")
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parser.set_defaults(output_dir="artiq_kasli")
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parser.add_argument("description", metavar="DESCRIPTION",
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parser.add_argument("description", metavar="DESCRIPTION",
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help="JSON system description file")
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help="JSON system description file")
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parser.add_argument("--identifier-str", default=None,
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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help="Override ROM identifier")
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args = parser.parse_args()
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args = parser.parse_args()
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@ -271,7 +271,7 @@ def main():
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else:
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else:
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raise ValueError("Invalid base")
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raise ValueError("Invalid base")
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soc = cls(description, identifier_str=args.identifier_str, **soc_kasli_argdict(args))
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soc = cls(description, gateware_identifier_str=args.gateware_identifier_str, **soc_kasli_argdict(args))
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args.variant = description["variant"]
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args.variant = description["variant"]
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build_artiq_soc(soc, builder_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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@ -119,7 +119,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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}
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}
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mem_map.update(MiniSoC.mem_map)
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, identifier_str=None, **kwargs):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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@ -129,7 +129,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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ethmac_ntxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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add_identifier(self, identifier_str=identifier_str)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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self.platform.toolchain.bitstream_commands.extend([
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@ -416,7 +416,7 @@ def main():
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help="variant: "
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help="variant: "
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"nist_clock/nist_qc2/sma_spi "
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"nist_clock/nist_qc2/sma_spi "
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"(default: %(default)s)")
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"(default: %(default)s)")
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parser.add_argument("--identifier-str", default=None,
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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help="Override ROM identifier")
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args = parser.parse_args()
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args = parser.parse_args()
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@ -426,7 +426,7 @@ def main():
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except KeyError:
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(identifier_str=args.identifier_str, **soc_kc705_argdict(args))
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soc = cls(gateware_identifier_str=args.gateware_identifier_str, **soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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@ -38,7 +38,7 @@ class Master(MiniSoC, AMPSoC):
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}
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}
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mem_map.update(MiniSoC.mem_map)
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, identifier_str=None, **kwargs):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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@ -49,7 +49,7 @@ class Master(MiniSoC, AMPSoC):
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csr_address_width=15,
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csr_address_width=15,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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add_identifier(self, identifier_str=identifier_str)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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platform = self.platform
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platform = self.platform
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rtio_clk_freq = 150e6
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rtio_clk_freq = 150e6
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@ -164,11 +164,11 @@ def main():
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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parser.set_defaults(output_dir="artiq_metlino")
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parser.set_defaults(output_dir="artiq_metlino")
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parser.add_argument("--identifier-str", default=None,
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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help="Override ROM identifier")
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args = parser.parse_args()
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args = parser.parse_args()
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args.variant = "master"
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args.variant = "master"
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soc = Master(identifier_str=args.identifier_str, **soc_sdram_argdict(args))
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soc = Master(gateware_identifier_str=args.gateware_identifier_str, **soc_sdram_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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@ -52,7 +52,7 @@ class SatelliteBase(MiniSoC):
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}
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}
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mem_map.update(MiniSoC.mem_map)
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs):
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def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs):
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MiniSoC.__init__(self,
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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@ -61,7 +61,7 @@ class SatelliteBase(MiniSoC):
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ethmac_nrxslots=4,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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**kwargs)
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add_identifier(self, suffix=identifier_suffix, identifier_str=identifier_str)
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add_identifier(self, suffix=identifier_suffix, gateware_identifier_str=gateware_identifier_str)
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self.rtio_clk_freq = rtio_clk_freq
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self.rtio_clk_freq = rtio_clk_freq
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platform = self.platform
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platform = self.platform
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@ -426,7 +426,7 @@ def main():
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help="Change type of signal generator. This is used exclusively for "
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help="Change type of signal generator. This is used exclusively for "
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"development and debugging.")
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"development and debugging.")
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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parser.add_argument("--identifier-str", default=None,
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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help="Override ROM identifier")
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args = parser.parse_args()
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args = parser.parse_args()
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@ -436,13 +436,13 @@ def main():
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with_sfp=args.sfp,
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with_sfp=args.sfp,
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jdcg_type=args.jdcg_type,
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jdcg_type=args.jdcg_type,
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with_wrpll=args.with_wrpll,
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with_wrpll=args.with_wrpll,
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identifier_str=args.identifier_str,
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gateware_identifier_str=args.gateware_identifier_str,
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**soc_sayma_amc_argdict(args))
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**soc_sayma_amc_argdict(args))
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elif variant == "simplesatellite":
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elif variant == "simplesatellite":
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soc = SimpleSatellite(
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soc = SimpleSatellite(
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with_sfp=args.sfp,
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with_sfp=args.sfp,
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with_wrpll=args.with_wrpll,
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with_wrpll=args.with_wrpll,
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identifier_str=args.identifier_str,
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gateware_identifier_str=args.gateware_identifier_str,
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**soc_sayma_amc_argdict(args))
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**soc_sayma_amc_argdict(args))
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else:
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else:
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raise SystemExit("Invalid variant (-V/--variant)")
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raise SystemExit("Invalid variant (-V/--variant)")
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@ -75,11 +75,11 @@ class _SatelliteBase(BaseSoC):
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}
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}
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mem_map.update(BaseSoC.mem_map)
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq, *, with_wrpll, identifier_str, **kwargs):
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def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs):
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BaseSoC.__init__(self,
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BaseSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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**kwargs)
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**kwargs)
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add_identifier(self, identifier_str=identifier_str)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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self.rtio_clk_freq = rtio_clk_freq
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self.rtio_clk_freq = rtio_clk_freq
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platform = self.platform
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platform = self.platform
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@ -299,7 +299,7 @@ def main():
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parser.add_argument("--rtio-clk-freq",
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parser.add_argument("--rtio-clk-freq",
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default=150, type=int, help="RTIO clock frequency in MHz")
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default=150, type=int, help="RTIO clock frequency in MHz")
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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parser.add_argument("--identifier-str", default=None,
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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help="Override ROM identifier")
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parser.set_defaults(output_dir=os.path.join("artiq_sayma", "rtm"))
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parser.set_defaults(output_dir=os.path.join("artiq_sayma", "rtm"))
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args = parser.parse_args()
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args = parser.parse_args()
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@ -307,7 +307,7 @@ def main():
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soc = Satellite(
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soc = Satellite(
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rtio_clk_freq=1e6*args.rtio_clk_freq,
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rtio_clk_freq=1e6*args.rtio_clk_freq,
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with_wrpll=args.with_wrpll,
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with_wrpll=args.with_wrpll,
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identifier_str=args.identifier_str,
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gateware_identifier_str=args.gateware_identifier_str,
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**soc_sayma_rtm_argdict(args))
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**soc_sayma_rtm_argdict(args))
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builder = SatmanSoCBuilder(soc, **builder_argdict(args))
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builder = SatmanSoCBuilder(soc, **builder_argdict(args))
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try:
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try:
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