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artiq/.travis.yml

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language: python
python:
- '3.4'
env:
global:
- MSCDIR=$TRAVIS_BUILD_DIR/misoc
- PATH=$HOME/miniconda/bin:/usr/local/llvm-or1k/bin:$PATH
- CC=gcc-4.7
- CXX=g++-4.7
- ARTIQ_NO_HARDWARE=1
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- secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws="
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before_install:
- echo "$TRAVIS_COMMIT_MSG" | grep -vq "\[soc\]"; export SOC=$?; true
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- ./.travis/get-toolchain.sh
- ./.travis/get-xilinx.sh
- ./.travis/get-anaconda.sh pip coverage numpy scipy sphinx h5py pyserial dateutil
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- source $HOME/miniconda/bin/activate py34
- sudo apt-get install --force-yes -y iverilog
- pip install --src . -e 'git+https://github.com/m-labs/migen.git@master#egg=migen'
- mkdir vpi
- iverilog-vpi --name=vpi/migensim migen/vpi/main.c migen/vpi/ipc.c
- git clone --recursive https://github.com/m-labs/misoc
- pip install --src . -e 'git+https://github.com/nist-ionstorage/llvmlite.git@artiq#egg=llvmlite'
- pip install coveralls
install:
- pip install -e .
script:
- coverage run --source=artiq setup.py test
- make -C doc/manual html
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- cd misoc; python make.py -X ../soc -t artiq build-headers build-bios; cd ..
- make -C soc/runtime
- if [ $SOC -ne 0 ]; then cd misoc python make.py -X ../soc -t artiq build-bitstream; cd ..; fi
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after_success:
coveralls
notifications:
email: false
irc:
channels:
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- chat.freenode.net#m-labs
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template:
- "%{repository}#%{build_number} (%{branch} - %{commit} : %{author}): %{message}"
- "Build details : %{build_url}"
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webhooks:
urls:
- https://webhooks.gitter.im/e/d26782523952bfa53814