removing core_io dependency

Co-authored-by: newell <newell.jensen@gmail.com>
Co-committed-by: newell <newell.jensen@gmail.com>

flake.lock

@@ -11,11 +11,11 @@
         "src-pythonparser": "src-pythonparser"
       },
       "locked": {
-        "lastModified": 1724411572,
-        "narHash": "sha256-33vj/pJ9iaVvaFP8uuBKMSQPN20mRlCbeBkTCNc9WB4=",
+        "lastModified": 1728269744,
+        "narHash": "sha256-GpVK5qyEnqcVDApRwD5wP3TlLVYj37XRJpN3KGb4mjU=",
         "ref": "refs/heads/master",
-        "rev": "352cf907ee67f7db5478fe23217cd5fcb7334617",
-        "revCount": 8996,
+        "rev": "049ef9022016f05119454335972d328b9e3ca539",
+        "revCount": 9022,
         "type": "git",
         "url": "https://github.com/m-labs/artiq.git"
       },
@@ -102,11 +102,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1723362943,
-        "narHash": "sha256-dFZRVSgmJkyM0bkPpaYRtG/kRMRTorUIDj8BxoOt1T4=",
+        "lastModified": 1727348695,
+        "narHash": "sha256-J+PeFKSDV+pHL7ukkfpVzCOO7mBSrrpJ3svwBFABbhI=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "a58bc8ad779655e790115244571758e8de055e3d",
+        "rev": "1925c603f17fc89f4c8f6bf6f631a802ad85d784",
         "type": "github"
       },
       "original": {
@@ -153,11 +153,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1717637367,
-        "narHash": "sha256-4mSm9wl5EMgzzrW6w86IDUevkEOT99FESHGcxcyQbD0=",
+        "lastModified": 1724921939,
+        "narHash": "sha256-/S5iip1LHLiCP2VY7PwClDteP9ZMRZvzzKR1LZuV3fs=",
         "owner": "m-labs",
         "repo": "sipyco",
-        "rev": "02b96ec2473a3c3d3c980899de2564ddce949dab",
+        "rev": "32ddd78ff3641b75054793ea0d5681c951766754",
         "type": "github"
       },
       "original": {
@@ -169,11 +169,11 @@
     "src-migen": {
       "flake": false,
       "locked": {
-        "lastModified": 1721561053,
-        "narHash": "sha256-z3LRhNmKZrjr6rFD0yxtccSa/SWvFIYmb+G/D5d2Jd8=",
+        "lastModified": 1727677091,
+        "narHash": "sha256-Zg3SQnTwMM/VkOGKogbPyuCC2NhLy8HB2SPEUWWNgCU=",
         "owner": "m-labs",
         "repo": "migen",
-        "rev": "9279e8623f8433bc4f23ac51e5e2331bfe544417",
+        "rev": "c19ae9f8ae162ffe2d310a92bfce53ac2a821bc8",
         "type": "github"
       },
       "original": {
@@ -240,11 +240,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1720537402,
-        "narHash": "sha256-ybvaQ48SVBqYVqgYmGUdefGZkni7PJ90qYQPHnFOwDs=",
+        "lastModified": 1728110308,
+        "narHash": "sha256-MAoFbcDgr+ZjptFCWfthK+tTnR1NcfuO6tvYhNM2Pwo=",
         "ref": "refs/heads/master",
-        "rev": "b2b3e5c933cbc4b7cb14adde480d7561a3ae71ee",
-        "revCount": 648,
+        "rev": "cc20478d91e30e1448a4304df7003caed2981b71",
+        "revCount": 651,
         "type": "git",
         "url": "https://git.m-labs.hk/m-labs/zynq-rs"
       },

flake.nix

@@ -75,7 +75,7 @@
 
       propagatedBuildInputs = with pkgs.python3Packages; [ setuptools click numpy toolz jinja2 ramda artiqpkgs.migen artiqpkgs.misoc ];
 
-      checkInputs = with pkgs.python3Packages; [ pytest-runner pytestCheckHook pytest-timeout ];
+      checkInputs = with pkgs.python3Packages; [ pytestCheckHook pytest-timeout ];
 
       # migen/misoc version checks are broken with pyproject for some reason
       postPatch = ''

src/Cargo.lock

@@ -229,7 +229,6 @@ name = "io"
 version = "0.0.0"
 dependencies = [
  "byteorder",
- "core_io",
  "libsupport_zynq",
 ]
 
@@ -239,7 +238,6 @@ version = "0.1.0"
 dependencies = [
  "build_zynq",
  "byteorder",
- "core_io",
  "cslice",
  "dwarf",
  "dyld",
@@ -278,7 +276,6 @@ name = "libboard_artiq"
 version = "0.0.0"
 dependencies = [
  "build_zynq",
- "core_io",
  "crc",
  "embedded-hal",
  "io",
@@ -519,7 +516,6 @@ dependencies = [
  "async-recursion",
  "build_zynq",
  "byteorder",
- "core_io",
  "cslice",
  "dwarf",
  "dyld",
@@ -559,7 +555,6 @@ name = "satman"
 version = "0.0.0"
 dependencies = [
  "build_zynq",
- "core_io",
  "cslice",
  "embedded-hal",
  "io",

src/gateware/ebaz4205.py

@@ -0,0 +1,253 @@
+#!/usr/bin/env python
+
+import argparse
+from operator import itemgetter
+
+from migen import *
+from migen.build.platforms import ebaz4205
+from migen.build.generic_platform import Pins, Subsignal, IOStandard, Misc
+from migen_axi.integration.soc_core import SoCCore
+from misoc.interconnect.csr import *
+
+from artiq.gateware import rtio
+from artiq.gateware.rtio.phy import ttl_simple
+from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
+
+import dma
+import analyzer
+
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
+
+_ps = [
+    (
+        "ps",
+        0,
+        Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
+        Subsignal("por_b", Pins("C7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
+        Subsignal("srst_b", Pins("B10"), IOStandard("LVCMOS18"), Misc("SLEW=FAST")),
+    )
+]
+
+_ddr = [
+    (
+        "ddr",
+        0,
+        Subsignal(
+            "a",
+            Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"),
+            IOStandard("SSTL15"),
+        ),
+        Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")),
+        Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")),
+        Subsignal("cke", Pins("N3"), IOStandard("SSTL15")),
+        Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")),
+        Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")),
+        Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")),
+        # Pins "T1 Y1" not connected
+        Subsignal("dm", Pins("A1 F1"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal(
+            "dq",
+            Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1"),
+            # Pins "P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3" not connected
+            IOStandard("SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal(
+            "dqs_n",
+            Pins("B2 F2"),  # Pins "T2 W4" not connected
+            IOStandard("DIFF_SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal(
+            "dqs_p",
+            Pins("C2 G2"),  # Pins "R2 W5" not connected
+            IOStandard("DIFF_SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15"), Misc("SLEW=FAST")),
+        Subsignal("odt", Pins("N5"), IOStandard("SSTL15")),
+        Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")),
+        Subsignal("we_n", Pins("M5"), IOStandard("SSTL15")),
+    )
+]
+
+# Connector J3
+_i2c = [
+    (
+        "i2c",
+        0,
+        Subsignal("scl", Pins("U12"), IOStandard("LVCMOS33")),
+        Subsignal("sda", Pins("V13"), IOStandard("LVCMOS33")),
+    )
+]
+
+
+class EBAZ4205(SoCCore):
+    def __init__(self, rtio_clk=125e6, acpki=False):
+        self.acpki = acpki
+
+        platform = ebaz4205.Platform()
+        platform.toolchain.bitstream_commands.extend(
+            [
+                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+            ]
+        )
+        platform.add_extension(_ps)
+        platform.add_extension(_ddr)
+        platform.add_extension(_i2c)
+
+        gmii = platform.request("gmii")
+        platform.add_period_constraint(gmii.rx_clk, 10)
+        platform.add_period_constraint(gmii.tx_clk, 10)
+        platform.add_platform_command(
+            "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
+        )
+
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
+        fix_serdes_timing_path(platform)
+        self.config["RTIO_FREQUENCY"] = str(rtio_clk / 1e6)
+        platform.add_period_constraint(self.ps7.cd_sys.clk, 10)
+
+        self.comb += [
+            self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk),
+            self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk),
+        ]
+        self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False)
+        self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False)
+        self.comb += [
+            ClockSignal("eth_rx").eq(gmii.rx_clk),
+            ClockSignal("eth_tx").eq(gmii.tx_clk),
+        ]
+        self.sync.eth_tx += [
+            gmii.txd.eq(self.ps7.enet0.enet.gmii.txd),
+            gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en),
+        ]
+        self.sync.eth_rx += [
+            self.ps7.enet0.enet.gmii.rxd.eq(gmii.rxd),
+            self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
+        ]
+
+        # MDIO
+        mdio = platform.request("mdio")
+        self.comb += mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc)
+        self.specials += Instance(
+            "IOBUF",
+            i_I=self.ps7.enet0.enet.mdio.o,
+            io_IO=mdio.mdio,
+            o_O=self.ps7.enet0.enet.mdio.i,
+            i_T=~self.ps7.enet0.enet.mdio.t_n,
+        )
+
+        # I2C
+        i2c = self.platform.request("i2c")
+        self.specials += [
+            # SCL
+            Instance(
+                "IOBUF",
+                i_I=self.ps7.i2c0.scl.o,
+                io_IO=i2c.scl,
+                o_O=self.ps7.i2c0.scl.i,
+                i_T=~self.ps7.i2c0.scl.t_n,
+            ),
+            # SDA
+            Instance(
+                "IOBUF",
+                i_I=self.ps7.i2c0.sda.o,
+                io_IO=i2c.sda,
+                o_O=self.ps7.i2c0.sda.i,
+                i_T=~self.ps7.i2c0.sda.t_n,
+            ),
+        ]
+
+        self.rtio_channels = []
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
+        self.csr_devices.append("rtio_core")
+        if self.acpki:
+            import acpki
+
+            self.config["KI_IMPL"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(
+                self.rtio_tsc,
+                bus=self.ps7.s_axi_acp,
+                user=self.ps7.s_axi_acp_user,
+                evento=self.ps7.event.o,
+            )
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri],
+            enable_routing=True,
+        )
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(
+            self.rtio_tsc, self.rtio_core.cri, self.ps7.s_axi_hp1
+        )
+        self.csr_devices.append("rtio_analyzer")
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner"
+    )
+    parser.add_argument(
+        "-r", default=None, help="build Rust interface into the specified file"
+    )
+    parser.add_argument(
+        "-m", default=None, help="build Rust memory interface into the specified file"
+    )
+    parser.add_argument(
+        "-c",
+        default=None,
+        help="build Rust compiler configuration into the specified file",
+    )
+    parser.add_argument(
+        "-g", default=None, help="build gateware into the specified directory"
+    )
+    parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)")
+    parser.add_argument(
+        "--acpki", default=False, action="store_true", help="enable ACPKI"
+    )
+    args = parser.parse_args()
+
+    soc = EBAZ4205(rtio_clk=int(args.rtio_clk), acpki=args.acpki)
+    soc.finalize()
+
+    if args.r is not None:
+        write_csr_file(soc, args.r)
+    if args.m is not None:
+        write_mem_file(soc, args.m)
+    if args.c is not None:
+        write_rustc_cfg_file(soc, args.c)
+    if args.g is not None:
+        soc.build(build_dir=args.g)
+
+
+if __name__ == "__main__":
+    main()

src/libboard_artiq/Cargo.toml.tpl

@@ -10,6 +10,7 @@ name = "libboard_artiq"
 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libconfig/target_zc706"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
+target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libconfig/target_ebaz4205"]
 calibrate_wrpll_skew = []
 
 [build-dependencies]
@@ -19,7 +20,6 @@ build_zynq = { path = "../libbuild_zynq" }
 log = "0.4"
 log_buffer = { version = "1.2" }
 crc = { version = "1.7", default-features = false }
-core_io = { version = "0.1", features = ["collections"] }
 embedded-hal = "0.2"
 nb = "1.0"
 void = { version = "1", default-features = false }

src/libboard_artiq/src/drtioaux.rs

@@ -1,9 +1,8 @@
 use core::slice;
 
-use core_io::{Error as IoError, ErrorKind as IoErrorKind};
 use crc;
 use io::{proto::{ProtoRead, ProtoWrite},
-         Cursor};
+         Cursor, Error as IoError};
 use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
 
 pub use crate::drtioaux_proto::Packet;
@@ -80,7 +79,7 @@ pub fn recv(linkno: u8) -> Result<Option<Packet>, Error> {
 
     receive(linkno, |buffer| {
         if buffer.len() < 8 {
-            return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into());
+            return Err(IoError::UnexpectedEnd).into());
         }
 
         let mut reader = Cursor::new(buffer);

src/libboard_artiq/src/drtioaux_async.rs

@@ -1,9 +1,8 @@
 use core::slice;
 
-use core_io::{Error as IoError, ErrorKind as IoErrorKind};
 use crc;
 use io::{proto::{ProtoRead, ProtoWrite},
-         Cursor};
+         Cursor, Error as IoError};
 use libasync::{block_async, task};
 use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
 use nb;
@@ -58,7 +57,7 @@ pub async fn recv(linkno: u8) -> Result<Option<Packet>, Error> {
 
     receive(linkno, |buffer| {
         if buffer.len() < 8 {
-            return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into());
+            return Err(IoError::UnexpectedEnd).into());
         }
 
         let mut reader = Cursor::new(buffer);

src/libboard_artiq/src/drtioaux_proto.rs

@@ -1,4 +1,4 @@
-use core_io::{Error as IoError, Read, Write};
+use io::{Error as IoError, Read, Write};
 use io::proto::{ProtoRead, ProtoWrite};
 
 const MAX_PACKET: usize = 1024;
@@ -10,13 +10,13 @@ pub const SAT_PAYLOAD_MAX_SIZE: usize  = /*max size*/MAX_PACKET - /*CRC*/4 - /*p
 pub const MASTER_PAYLOAD_MAX_SIZE: usize = SAT_PAYLOAD_MAX_SIZE - /*source*/1 - /*destination*/1 - /*ID*/4;
 
 #[derive(Debug)]
-pub enum Error {
+pub enum Error<T> {
     UnknownPacket(u8),
-    Io(IoError),
+    Io(IoError<T>),
 }
 
-impl From<IoError> for Error {
-    fn from(value: IoError) -> Error {
+impl<T> From<IoError<T>> for Error<T> {
+    fn from(value: IoError<T>) -> Error<T> {
         Error::Io(value)
     }
 }
@@ -290,7 +290,7 @@ pub enum Packet {
 }
 
 impl Packet {
-    pub fn read_from<R>(reader: &mut R) -> Result<Self, Error>
+    pub fn read_from<R>(reader: &mut R) -> Result<Self, Error<R::ReadError>>
     where R: Read + ?Sized {
         Ok(match reader.read_u8()? {
             0x00 => Packet::EchoRequest,
@@ -567,7 +567,7 @@ impl Packet {
         })
     }
 
-    pub fn write_to<W>(&self, writer: &mut W) -> Result<(), IoError>
+    pub fn write_to<W>(&self, writer: &mut W) -> Result<(), IoError<W::WriteError>>
     where W: Write + ?Sized {
         match *self {
             Packet::EchoRequest => writer.write_u8(0x00)?,

src/libboard_artiq/src/lib.rs

@@ -3,7 +3,6 @@
 #![feature(naked_functions)]
 #![feature(asm)]
 
-extern crate core_io;
 extern crate crc;
 extern crate embedded_hal;
 extern crate io;

src/libio/Cargo.toml.tpl

@@ -8,7 +8,6 @@ name = "io"
 path = "lib.rs"
 
 [dependencies]
-core_io = { version = "0.1", features = ["collections"] }
 byteorder = { version = "1.0", default-features = false, optional = true }
 
 libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }

src/libio/cursor.rs

@@ -1,7 +1,7 @@
 #[cfg(feature = "alloc")]
 use alloc::vec::Vec;
 
-use core_io::{Error as IoError, Read, Write};
+use crate::{Read, Write};
 
 #[derive(Debug, Clone)]
 pub struct Cursor<T> {
@@ -42,7 +42,9 @@ impl<T> Cursor<T> {
 }
 
 impl<T: AsRef<[u8]>> Read for Cursor<T> {
-    fn read(&mut self, buf: &mut [u8]) -> Result<usize, IoError> {
+    type ReadError = !;
+
+    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::ReadError> {
         let data = &self.inner.as_ref()[self.pos..];
         let len = buf.len().min(data.len());
         // ``copy_from_slice`` generates AXI bursts, use a regular loop instead
@@ -55,7 +57,10 @@ impl<T: AsRef<[u8]>> Read for Cursor<T> {
 }
 
 impl Write for Cursor<&mut [u8]> {
-    fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
+    type WriteError = !;
+    type FlushError = !;
+
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::WriteError> {
         let data = &mut self.inner[self.pos..];
         let len = buf.len().min(data.len());
         for i in 0..len {
@@ -66,20 +71,23 @@ impl Write for Cursor<&mut [u8]> {
     }
 
     #[inline]
-    fn flush(&mut self) -> Result<(), IoError> {
+    fn flush(&mut self) -> Result<(), Self::FlushError> {
         Ok(())
     }
 }
 
 #[cfg(feature = "alloc")]
 impl Write for Cursor<Vec<u8>> {
-    fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
+    type WriteError = !;
+    type FlushError = !;
+
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::WriteError> {
         self.inner.extend_from_slice(buf);
         Ok(buf.len())
     }
 
     #[inline]
-    fn flush(&mut self) -> Result<(), IoError> {
+    fn flush(&mut self) -> Result<(), Self::FlushError> {
         Ok(())
     }
 }

src/libio/lib.rs

@@ -3,7 +3,6 @@
 
 #[cfg(feature = "alloc")]
 extern crate alloc;
-extern crate core_io;
 
 #[cfg(feature = "byteorder")]
 extern crate byteorder;
@@ -17,3 +16,126 @@ pub use cursor::Cursor;
 pub use proto::ReadStringError;
 #[cfg(feature = "byteorder")]
 pub use proto::{ProtoRead, ProtoWrite};
+
+#[derive(Debug, Clone, PartialEq)]
+pub enum Error<T> {
+    UnexpectedEnd,
+    Other(T),
+}
+
+impl<T> From<T> for Error<T> {
+    fn from(value: T) -> Error<T> {
+        Error::Other(value)
+    }
+}
+
+pub trait Read {
+    type ReadError;
+
+    /// Pull some bytes from this source into the specified buffer, returning
+    /// how many bytes were read.
+    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::ReadError>;
+
+    /// Read the exact number of bytes required to fill `buf`.
+    fn read_exact(&mut self, mut buf: &mut [u8]) -> Result<(), Error<Self::ReadError>> {
+        while !buf.is_empty() {
+            let read_bytes = self.read(buf)?;
+            if read_bytes == 0 {
+                return Err(Error::UnexpectedEnd);
+            }
+
+            buf = &mut { buf }[read_bytes..];
+        }
+
+        Ok(())
+    }
+}
+
+impl<'a, T: Read> Read for &'a mut T {
+    type ReadError = T::ReadError;
+
+    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::ReadError> {
+        T::read(self, buf)
+    }
+}
+
+pub trait Write {
+    type WriteError;
+    type FlushError;
+
+    /// Write a buffer into this object, returning how many bytes were written.
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::WriteError>;
+
+    /// Flush this output stream, ensuring that all intermediately buffered contents
+    /// reach their destination.
+    fn flush(&mut self) -> Result<(), Self::FlushError>;
+
+    /// Attempts to write an entire buffer into `self`.
+    fn write_all(&mut self, mut buf: &[u8]) -> Result<(), Error<Self::WriteError>> {
+        while buf.len() > 0 {
+            let written_bytes = self.write(buf)?;
+            if written_bytes == 0 {
+                return Err(Error::UnexpectedEnd);
+            }
+
+            buf = &buf[written_bytes..];
+        }
+
+        Ok(())
+    }
+
+    /// Hints the writer how much bytes will be written after call to this function.
+    ///
+    /// At least `min` bytes should be written after the call to this function and
+    /// if `max` is `Some(x)` than at most `x` bytes should be written.
+    fn size_hint(&mut self, _min: usize, _max: Option<usize>) {}
+}
+
+impl<'a, T: Write> Write for &'a mut T {
+    type WriteError = T::WriteError;
+    type FlushError = T::FlushError;
+
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::WriteError> {
+        T::write(self, buf)
+    }
+
+    fn flush(&mut self) -> Result<(), Self::FlushError> {
+        T::flush(self)
+    }
+
+    fn size_hint(&mut self, min: usize, max: Option<usize>) {
+        T::size_hint(self, min, max)
+    }
+}
+
+impl<'a> Write for &'a mut [u8] {
+    type WriteError = !;
+    type FlushError = !;
+
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::WriteError> {
+        let len = buf.len().min(self.len());
+        self[..len].copy_from_slice(&buf[..len]);
+        Ok(len)
+    }
+
+    #[inline]
+    fn flush(&mut self) -> Result<(), Self::FlushError> {
+        Ok(())
+    }
+}
+
+#[cfg(feature = "alloc")]
+impl<'a> Write for alloc::vec::Vec<u8> {
+    type WriteError = !;
+    type FlushError = !;
+
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::WriteError> {
+        self.extend_from_slice(buf);
+        Ok(buf.len())
+    }
+
+    #[inline]
+    fn flush(&mut self) -> Result<(), Self::FlushError> {
+        Ok(())
+    }
+}

src/libio/proto.rs

@@ -3,7 +3,9 @@ use alloc::{string::String, vec};
 use core::str::Utf8Error;
 
 use byteorder::{ByteOrder, NativeEndian};
-use core_io::{Error as IoError, Read, Write};
+use Error as IoError;
+use Read;
+use Write;
 
 #[allow(dead_code)]
 #[derive(Debug, Clone, PartialEq)]
@@ -147,7 +149,7 @@ pub trait ProtoWrite {
 impl<T> ProtoRead for T
 where T: Read + ?Sized
 {
-    type ReadError = IoError;
+    type ReadError = IoError<T::ReadError>;
 
     fn read_exact(&mut self, buf: &mut [u8]) -> Result<(), Self::ReadError> {
         T::read_exact(self, buf)
@@ -157,7 +159,7 @@ where T: Read + ?Sized
 impl<T> ProtoWrite for T
 where T: Write + ?Sized
 {
-    type WriteError = IoError;
+    type WriteError = IoError<T::WriteError>;
 
     fn write_all(&mut self, buf: &[u8]) -> Result<(), Self::WriteError> {
         T::write_all(self, buf)

src/libksupport/Cargo.toml.tpl

@@ -12,7 +12,6 @@ build_zynq = { path = "../libbuild_zynq" }
 cslice = "0.3"
 log = "0.4"
 nb = "0.1"
-core_io = { version = "0.1", features = ["collections"] }
 byteorder = { version = "1.3", default-features = false }
 void = { version = "1", default-features = false }
 log_buffer = { version = "1.2" }

src/libksupport/src/eh_artiq.rs

@@ -14,10 +14,9 @@
 
 use core::mem;
 
-use core_io::Error as ReadError;
 use cslice::{AsCSlice, CSlice};
 use dwarf::eh::{self, EHAction, EHContext};
-use io::{Cursor, ProtoRead};
+use io::{Cursor, Error as ReadError, ProtoRead, Read};
 use libc::{c_int, c_void, uintptr_t};
 use log::{error, trace};
 use unwind as uw;
@@ -295,7 +294,9 @@ pub unsafe extern "C" fn raise(exception: *const Exception) -> ! {
     unreachable!();
 }
 
-fn read_exception_string<'a>(reader: &mut Cursor<&[u8]>) -> Result<CSlice<'a, u8>, ReadError> {
+fn read_exception_string<'a, 'b>(
+    reader: &mut Cursor<&'b [u8]>,
+) -> Result<CSlice<'a, u8>, ReadError<<Cursor<&'b [u8]> as Read>::ReadError>> {
     let len = reader.read_u32()? as usize;
     if len == usize::MAX {
         let data = reader.read_u32()?;
@@ -311,7 +312,7 @@ fn read_exception_string<'a>(reader: &mut Cursor<&[u8]>) -> Result<CSlice<'a, u8
     }
 }
 
-fn read_exception(raw_exception: &[u8]) -> Result<Exception, ReadError> {
+fn read_exception(raw_exception: &[u8]) -> Result<Exception, ReadError<<Cursor<&[u8]> as Read>::ReadError>> {
     let mut reader = Cursor::new(raw_exception);
 
     let mut byte = reader.read_u8()?;

src/libksupport/src/rpc.rs

@@ -1,9 +1,8 @@
 use core::str;
 
 use byteorder::{ByteOrder, NativeEndian};
-use core_io::{Error, Read, Write};
 use cslice::{CMutSlice, CSlice};
-use io::{ProtoRead, ProtoWrite};
+use io::{Error, ProtoRead, ProtoWrite, Read, Write};
 use log::trace;
 
 use self::tag::{split_tag, Tag, TagIterator};
@@ -37,16 +36,17 @@ pub unsafe fn align_ptr_mut<T>(ptr: *mut ()) -> *mut T {
 
 // versions for reader rather than TcpStream
 // they will be made into sync for satellite subkernels later
-unsafe fn recv_elements<F, R>(
+unsafe fn recv_elements<F, R, E>(
     reader: &mut R,
     elt_tag: Tag,
     length: usize,
     storage: *mut (),
     alloc: &mut F,
-) -> Result<(), Error>
+) -> Result<(), E>
 where
     F: FnMut(usize) -> *mut (),
     R: Read + ?Sized,
+    E: From<Error<R::ReadError>>,
 {
     match elt_tag {
         Tag::Bool => {
@@ -79,10 +79,11 @@ where
     Ok(())
 }
 
-unsafe fn recv_value<F, R>(reader: &mut R, tag: Tag, data: &mut *mut (), alloc: &mut F) -> Result<(), Error>
+unsafe fn recv_value<F, R, E>(reader: &mut R, tag: Tag, data: &mut *mut (), alloc: &mut F) -> Result<(), E>
 where
     F: FnMut(usize) -> *mut (),
     R: Read + ?Sized,
+    E: From<Error<R::ReadError>>,
 {
     macro_rules! consume_value {
         ($ty:ty, | $ptr:ident | $map:expr) => {{
@@ -175,15 +176,16 @@ where
     }
 }
 
-pub fn recv_return<'a, F, R>(
+pub fn recv_return<'a, F, R, E>(
     reader: &mut R,
     tag_bytes: &'a [u8],
     data: *mut (),
     alloc: &mut F,
-) -> Result<&'a [u8], Error>
+) -> Result<&'a [u8], E>
 where
     F: FnMut(usize) -> *mut (),
     R: Read + ?Sized,
+    E: From<Error<R::ReadError>>,
 {
     let mut it = TagIterator::new(tag_bytes);
     trace!("recv ...->{}", it);
@@ -201,7 +203,7 @@ unsafe fn send_elements<W>(
     length: usize,
     data: *const (),
     write_tags: bool,
-) -> Result<(), Error>
+) -> Result<(), Error<W::WriteError>>
 where
     W: Write + ?Sized,
 {
@@ -233,8 +235,15 @@ where
     Ok(())
 }
 
-unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const (), write_tags: bool) -> Result<(), Error>
-where W: Write + ?Sized {
+unsafe fn send_value<W>(
+    writer: &mut W,
+    tag: Tag,
+    data: &mut *const (),
+    write_tags: bool,
+) -> Result<(), Error<W::WriteError>>
+where
+    W: Write + ?Sized,
+{
     macro_rules! consume_value {
         ($ty:ty, | $ptr:ident | $map:expr) => {{
             let $ptr = align_ptr::<$ty>(*data);
@@ -337,7 +346,7 @@ pub fn send_args<W>(
     tag_bytes: &[u8],
     data: *const *const (),
     write_tags: bool,
-) -> Result<(), Error>
+) -> Result<(), Error<W::WriteError>>
 where
     W: Write + ?Sized,
 {

src/runtime/Cargo.toml.tpl

@@ -8,6 +8,7 @@ edition = "2018"
 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"]
+target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205", "libboard_artiq/target_ebaz4205"]
 default = ["target_zc706"]
 
 [build-dependencies]
@@ -19,7 +20,6 @@ num-derive = "0.3"
 cslice = "0.3"
 log = "0.4"
 embedded-hal = "0.2"
-core_io = { version = "0.1", features = ["collections"] }
 byteorder = { version = "1.3", default-features = false }
 void = { version = "1", default-features = false }
 futures = { version = "0.3", default-features = false, features = ["async-await"] }

src/runtime/src/comms.rs

@@ -1,12 +1,12 @@
 use alloc::{collections::BTreeMap, rc::Rc, string::String, vec, vec::Vec};
 use core::{cell::RefCell, fmt, slice, str};
 
-use core_io::Error as IoError;
 use cslice::CSlice;
 use dyld::elf;
 use futures::{future::FutureExt, select_biased};
 #[cfg(has_drtio)]
 use io::Cursor;
+use io::Error as IoError;
 #[cfg(has_drtio)]
 use ksupport::rpc;
 use ksupport::{kernel, resolve_channel_name};
@@ -78,8 +78,8 @@ impl From<smoltcp::Error> for Error {
     }
 }
 
-impl From<IoError> for Error {
-    fn from(_error: IoError) -> Self {
+impl<T> From<IoError<T>> for Error {
+    fn from(_error: IoError<T>) -> Self {
         Error::IoError
     }
 }

src/runtime/src/rtio_clocking.rs

@@ -1,6 +1,8 @@
+#[cfg(not(feature = "target_ebaz4205"))]
 use embedded_hal::blocking::delay::DelayMs;
 #[cfg(has_si5324)]
 use ksupport::i2c;
+#[cfg(not(feature = "target_ebaz4205"))]
 use libboard_artiq::pl;
 #[cfg(has_si5324)]
 use libboard_artiq::si5324;
@@ -10,7 +12,9 @@ use libboard_artiq::si549;
 use libboard_zynq::i2c::I2c;
 use libboard_zynq::timer::GlobalTimer;
 use libconfig::Config;
-use log::{info, warn};
+#[cfg(not(feature = "target_ebaz4205"))]
+use log::info;
+use log::warn;
 
 #[derive(Debug, PartialEq, Copy, Clone)]
 #[allow(non_camel_case_types)]
@@ -69,7 +73,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
     res
 }
 
-#[cfg(not(has_drtio))]
+#[cfg(not(any(has_drtio, feature = "target_ebaz4205")))]
 fn init_rtio(timer: &mut GlobalTimer) {
     info!("Switching SYS clocks...");
     unsafe {
@@ -429,7 +433,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
     #[cfg(has_drtio)]
     init_drtio(timer);
 
-    #[cfg(not(has_drtio))]
+    #[cfg(not(any(has_drtio, feature = "target_ebaz4205")))]
     init_rtio(timer);
 
     #[cfg(all(has_si549, has_wrpll))]

src/satman/Cargo.toml.tpl

@@ -15,7 +15,6 @@ build_zynq = { path = "../libbuild_zynq" }
 
 [dependencies]
 log = { version = "0.4", default-features = false }
-core_io = { version = "0.1", features = ["collections"] }
 cslice = "0.3"
 embedded-hal = "0.2"
 

src/satman/src/main.rs

@@ -4,7 +4,6 @@
 
 #[macro_use]
 extern crate log;
-extern crate core_io;
 extern crate cslice;
 extern crate embedded_hal;
 

src/satman/src/subkernel.rs

@@ -4,10 +4,9 @@ use alloc::{collections::BTreeMap,
             vec::Vec};
 use core::{option::NoneError, slice, str};
 
-use core_io::{Error as IoError, Write};
 use cslice::AsCSlice;
 use dma::{Error as DmaError, Manager as DmaManager};
-use io::{Cursor, ProtoWrite};
+use io::{Cursor, Error as IoError, ProtoWrite, Write};
 use ksupport::{eh_artiq, kernel, rpc};
 use libboard_artiq::{drtio_routing::RoutingTable,
                      drtioaux,