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artiq-zynq
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extremely wip

This commit is contained in:
Simon Renblad 2024-09-02 17:08:00 +08:00
parent 049d0f2caa
commit b485bf16a7
2 changed files with 10 additions and 5 deletions
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10
src/runtime/src/comms.rs
View File

@ -861,7 +861,9 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
// keep yielding // keep yielding
}) => (), }) => (),
_ = terminate.async_wait().fuse() => (), _ = terminate.async_wait().fuse() => (),
_ = restart_idle.async_wait().fuse() => () _ = async {
restart_idle.async_wait().fuse(),
}
} }
connection.signal(); connection.signal();
}); });
@ -926,8 +928,10 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
load_and_run_idle_kernel(&buffer, &control, &up_destinations, &aux_mutex, &routing_table, timer).await; load_and_run_idle_kernel(&buffer, &control, &up_destinations, &aux_mutex, &routing_table, timer).await;
} }
}).fuse() => (), }).fuse() => (),
_ = terminate.async_wait().fuse() => (), _ = (async {
_ = restart_idle.async_wait().fuse() => () restart_idle.0.async_wait().await;
restart_idle.1.signal();
}).fuse() => (),
} }
drop(_lock); drop(_lock);
} }

5
src/runtime/src/mgmt.rs
View File

@ -201,10 +201,11 @@ async fn handle_connection(stream: &mut TcpStream, pull_id: Rc<RefCell<u32>>, cf
let value = cfg.write(&key, buffer); let value = cfg.write(&key, buffer);
if value.is_ok() { if value.is_ok() {
debug!("write success"); debug!("write success");
write_i8(stream, Reply::Success as i8).await?;
if key == "idle_kernel" { if key == "idle_kernel" {
restart_idle.signal(); restart_idle.1.async_wait().await?;
restart_idle.0.signal();
} }
write_i8(stream, Reply::Success as i8).await?;
} else { } else {
// this is an error because we do not expect write to fail // this is an error because we do not expect write to fail
error!("failed to write: {:?}", value); error!("failed to write: {:?}", value);