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dma: fix inflight_cnt and eop generation

This commit is contained in:
Sebastien Bourdeauducq 2020-07-13 18:51:55 +08:00
parent fa2d71615a
commit 5c3c3c26b5
2 changed files with 10 additions and 3 deletions

View File

@ -42,13 +42,20 @@ class AXIReader(Module):
# UG585: "Large slave interface read acceptance capability in the range of 14 to 70 commands" # UG585: "Large slave interface read acceptance capability in the range of 14 to 70 commands"
inflight_cnt = Signal(max=128) inflight_cnt = Signal(max=128)
self.sync += inflight_cnt.eq(inflight_cnt + (ar.valid & ar.ready) - (r.valid & r.ready)) request_done = Signal()
reply_done = Signal()
self.comb += [
request_done.eq(ar.valid & ar.ready),
reply_done.eq(r.valid & r.ready & r.last)
]
self.sync += inflight_cnt.eq(inflight_cnt + request_done - reply_done)
self.comb += [ self.comb += [
self.source.stb.eq(r.valid), self.source.stb.eq(r.valid),
r.ready.eq(self.source.ack), r.ready.eq(self.source.ack),
self.source.data.eq(r.data), self.source.data.eq(r.data),
self.source.eop.eq(eop_pending & r.last & (inflight_cnt == 0)) # Note that when eop_pending=1, no new transactions are made and inflight_cnt is no longer incremented
self.source.eop.eq(eop_pending & r.last & (inflight_cnt == 1))
] ]

View File

@ -45,7 +45,7 @@ class AXIMemorySim:
raise ValueError raise ValueError
addr = request.addr//self.align + i addr = request.addr//self.align + i
if addr < len(self.queue): if addr < len(self.queue):
data = self.queue[addr] data = self.data[addr]
else: else:
data = 0 data = 0
yield from self.bus.write_r(request.id, data, last=i == request_len-1) yield from self.bus.write_r(request.id, data, last=i == request_len-1)