forked from M-Labs/artiq-zynq
use logging
This commit is contained in:
parent
79846504bd
commit
4cb73f32aa
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@ -3,12 +3,12 @@ use core::fmt;
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use core::cmp::min;
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use core::cmp::min;
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use core::cell::RefCell;
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use core::cell::RefCell;
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use alloc::rc::Rc;
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use alloc::rc::Rc;
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use log::{warn, error};
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use num_derive::{FromPrimitive, ToPrimitive};
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use num_derive::{FromPrimitive, ToPrimitive};
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use num_traits::{FromPrimitive, ToPrimitive};
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use num_traits::{FromPrimitive, ToPrimitive};
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use libboard_zynq::{
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use libboard_zynq::{
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println,
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self as zynq,
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self as zynq,
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smoltcp::{
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smoltcp::{
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self,
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self,
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@ -185,7 +185,7 @@ async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Contr
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write_chunk(&stream, b"core1 failed to process data").await?;
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write_chunk(&stream, b"core1 failed to process data").await?;
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},
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},
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_ => {
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_ => {
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println!("received unexpected message from core1: {:?}", reply);
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error!("received unexpected message from core1: {:?}", reply);
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write_header(&stream, Reply::LoadFailed).await?;
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write_header(&stream, Reply::LoadFailed).await?;
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write_chunk(&stream, b"core1 sent unexpected reply").await?;
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write_chunk(&stream, b"core1 sent unexpected reply").await?;
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}
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}
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@ -250,7 +250,7 @@ pub fn main() {
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task::spawn(async {
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task::spawn(async {
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let _ = handle_connection(&stream, control)
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let _ = handle_connection(&stream, control)
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.await
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.await
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.map_err(|e| println!("Connection: {}", e));
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.map_err(|e| warn!("Connection: {}", e));
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let _ = stream.flush().await;
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let _ = stream.flush().await;
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let _ = stream.abort().await;
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let _ = stream.abort().await;
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});
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});
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@ -1,7 +1,7 @@
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use log::{debug, error};
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use alloc::{vec, vec::Vec, sync::Arc};
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use alloc::{vec, vec::Vec, sync::Arc};
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use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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use libboard_zynq::println;
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use libsupport_zynq::boot::Core1;
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use libsupport_zynq::boot::Core1;
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use dyld;
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use dyld;
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@ -93,7 +93,7 @@ fn resolve(required: &[u8]) -> Option<u32> {
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#[no_mangle]
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#[no_mangle]
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pub fn main_core1() {
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pub fn main_core1() {
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println!("Core1 started");
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debug!("Core1 started");
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let mut core1_tx = None;
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let mut core1_tx = None;
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while core1_tx.is_none() {
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while core1_tx.is_none() {
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@ -116,12 +116,12 @@ pub fn main_core1() {
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core1_tx.send(Message::LoadCompleted)
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core1_tx.send(Message::LoadCompleted)
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},
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},
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Err(error) => {
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Err(error) => {
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println!("failed to load shared library: {}", error);
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error!("failed to load shared library: {}", error);
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core1_tx.send(Message::LoadFailed)
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core1_tx.send(Message::LoadFailed)
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}
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}
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}
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}
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},
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},
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_ => println!("Core1 received unexpected message: {:?}", message),
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_ => error!("Core1 received unexpected message: {:?}", message),
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}
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}
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}
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}
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}
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}
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@ -5,9 +5,9 @@ extern crate alloc;
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extern crate log;
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extern crate log;
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use core::{cmp, str};
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use core::{cmp, str};
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use log::info;
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use libboard_zynq::{
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use libboard_zynq::{
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println,
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self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
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self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
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};
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};
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use libsupport_zynq::{logger, ram};
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use libsupport_zynq::{logger, ram};
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@ -33,9 +33,9 @@ fn identifier_read(buf: &mut [u8]) -> &str {
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#[no_mangle]
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#[no_mangle]
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pub fn main_core0() {
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pub fn main_core0() {
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println!("ARTIQ runtime starting...");
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let _ = logger::init();
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let _ = logger::init();
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log::set_max_level(log::LevelFilter::Debug);
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log::set_max_level(log::LevelFilter::Debug);
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info!("NAR3 starting...");
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const CPU_FREQ: u32 = 800_000_000;
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const CPU_FREQ: u32 = 800_000_000;
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@ -46,7 +46,7 @@ pub fn main_core0() {
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let mut ddr = zynq::ddr::DdrRam::new();
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let mut ddr = zynq::ddr::DdrRam::new();
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ram::init_alloc(&mut ddr);
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ram::init_alloc(&mut ddr);
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println!("Detected gateware: {}", identifier_read(&mut [0; 64]));
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info!("Detected gateware: {}", identifier_read(&mut [0; 64]));
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comms::main();
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comms::main();
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}
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}
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@ -1,7 +1,6 @@
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use core::ptr::{read_volatile, write_volatile};
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use core::ptr::{read_volatile, write_volatile};
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use cslice::CSlice;
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use cslice::CSlice;
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use log::error;
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use libboard_zynq::println;
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use crate::pl::csr;
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use crate::pl::csr;
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@ -56,12 +55,12 @@ unsafe fn process_exceptional_status(channel: i32, status: u8) {
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while csr::rtio::o_status_read() & RTIO_O_STATUS_WAIT != 0 {}
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while csr::rtio::o_status_read() & RTIO_O_STATUS_WAIT != 0 {}
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}
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}
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if status & RTIO_O_STATUS_UNDERFLOW != 0 {
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if status & RTIO_O_STATUS_UNDERFLOW != 0 {
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println!("RTIO underflow at {0} mu, channel {1}, slack {2} mu",
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error!("RTIO underflow at {0} mu, channel {1}, slack {2} mu",
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timestamp, channel as i64, timestamp - get_counter());
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timestamp, channel as i64, timestamp - get_counter());
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}
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}
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if status & RTIO_O_STATUS_DESTINATION_UNREACHABLE != 0 {
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if status & RTIO_O_STATUS_DESTINATION_UNREACHABLE != 0 {
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println!("RTIO destination unreachable, output, at {0} mu, channel {1}",
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error!("RTIO destination unreachable, output, at {0} mu, channel {1}",
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timestamp, channel as i64);
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timestamp, channel as i64);
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}
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}
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}
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}
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@ -103,15 +102,15 @@ pub extern fn input_timestamp(timeout: i64, channel: i32) -> i64 {
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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csr::rtio::i_overflow_reset_write(1);
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println!("RTIO input overflow on channel {0}",
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error!("RTIO input overflow on channel {0}",
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channel as i64);
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channel as i64);
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}
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}
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if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
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if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
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return -1
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return -1
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}
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}
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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println!("RTIO destination unreachable, input, on channel {0}",
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error!("RTIO destination unreachable, input, on channel {0}",
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channel as i64);
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channel as i64);
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}
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}
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csr::rtio::i_timestamp_read() as i64
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csr::rtio::i_timestamp_read() as i64
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@ -130,12 +129,12 @@ pub extern fn input_data(channel: i32) -> i32 {
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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csr::rtio::i_overflow_reset_write(1);
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println!("RTIO input overflow on channel {0}",
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error!("RTIO input overflow on channel {0}",
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channel as i64);
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channel as i64);
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}
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}
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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println!("RTIO destination unreachable, input, on channel {0}",
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error!("RTIO destination unreachable, input, on channel {0}",
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channel as i64);
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channel as i64);
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}
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}
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rtio_i_data_read(0) as i32
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rtio_i_data_read(0) as i32
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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csr::rtio::i_overflow_reset_write(1);
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println!("RTIO input overflow on channel {0}",
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error!("RTIO input overflow on channel {0}",
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channel as i64);
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channel as i64);
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}
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}
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if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
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if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
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return TimestampedData { timestamp: -1, data: 0 }
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return TimestampedData { timestamp: -1, data: 0 }
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}
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}
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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println!("RTIO destination unreachable, input, on channel {0}",
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error!("RTIO destination unreachable, input, on channel {0}",
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channel as i64);
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channel as i64);
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}
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}
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TimestampedData {
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TimestampedData {
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