forked from M-Labs/zynq-rs
147 lines
3.7 KiB
Rust
147 lines
3.7 KiB
Rust
use r0::zero_bss;
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use libregister::{
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VolatileCell,
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RegisterR, RegisterW, RegisterRW,
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};
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use libcortex_a9::{asm, regs::*, cache, mmu};
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use libboard_zynq::{slcr, mpcore};
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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static mut __stack_start: u32;
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}
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/// `0` means: wait for initialization by core0
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static mut CORE1_STACK: VolatileCell<u32> = VolatileCell::new(0);
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_MASK: u32 = 0x3;
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match MPIDR.read() & CORE_MASK {
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0 => {
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SP.write(&mut __stack_start as *mut _ as u32);
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boot_core0();
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}
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1 => {
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while CORE1_STACK.get() == 0 {
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asm::wfe();
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}
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SP.write(CORE1_STACK.get());
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boot_core1();
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}
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_ => unreachable!(),
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}
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}
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#[naked]
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#[inline(never)]
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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let mpcore = mpcore::RegisterBlock::new();
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mpcore.scu_invalidate.invalidate_all_cores();
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zero_bss(&mut __bss_start, &mut __bss_end);
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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mpcore.scu_control.start();
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ACTLR.enable_smp();
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// TODO: Barriers reqd when core1 is not yet starting?
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asm::dmb();
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asm::dsb();
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crate::main();
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panic!("return from main");
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});
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}
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#[naked]
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#[inline(never)]
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unsafe fn boot_core1() -> ! {
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l1_cache_init();
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let mpcore = mpcore::RegisterBlock::new();
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mpcore.scu_invalidate.invalidate_core1();
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let mmu_table = mmu::L1Table::get();
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mmu::with_mmu(mmu_table, || {
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ACTLR.enable_smp();
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// TODO: Barriers reqd when core1 is not yet starting?
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asm::dmb();
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asm::dsb();
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crate::main_core1();
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panic!("return from main_core1");
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});
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}
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fn l1_cache_init() {
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use libcortex_a9::cache::*;
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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//
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// NOTE: It is both faster and correct to only invalidate instead
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// of also flush the cache (as was done before with
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// `dccisw()`) and it is correct to perform this operation
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// for all of the L1 data cache rather than a (previously
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// unspecified) combination of one cache set and one cache
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// way.
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dciall();
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}
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pub struct Core1<S: AsMut<[u32]>> {
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pub stack: S,
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}
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impl<S: AsMut<[u32]>> Core1<S> {
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pub fn stop(&self) {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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});
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}
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/// Reset and start core1
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///
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/// The stack must not be in OCM because core1 still has to
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/// initialize its MMU before it can access DDR.
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pub fn start(stack: S) -> Self {
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let mut core = Core1 { stack };
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// reset and stop (safe to repeat)
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core.stop();
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let stack = core.stack.as_mut();
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let stack_start = &mut stack[stack.len() - 1];
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unsafe {
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CORE1_STACK.set(stack_start as *mut _ as u32);
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}
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// Ensure stack pointer has been written to cache
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asm::dmb();
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// Flush cache-line
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cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as u32);
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// wake up core1
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
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});
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core
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}
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}
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