forked from M-Labs/zynq-rs
40 lines
984 B
Rust
40 lines
984 B
Rust
use crate::regs::RegisterW;
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use super::slcr;
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use super::clocks::CpuClocks;
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/// Micron MT41J256M8HX-15E: 667 MHz
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const DDR_FREQ: u32 = 666_666_666;
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pub struct DdrRam {
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}
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impl DdrRam {
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pub fn new() -> Self {
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Self::clock_setup();
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let ram = DdrRam {};
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// TODO: ram.
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ram
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}
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fn clock_setup() {
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let clocks = CpuClocks::get();
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.ddr_pll_ctrl.write(
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slcr::PllCtrl::zeroed()
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);
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slcr.ddr_clk_ctrl.write(
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slcr::DdrClkCtrl::zeroed()
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.ddr_2xclkact(true)
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.ddr_3xclkact(true)
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.ddr_2xclk_divisor(ddr2x_clk_divisor)
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.ddr_3xclk_divisor(ddr3x_clk_divisor)
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);
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});
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}
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}
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