forked from M-Labs/zynq-rs
113 lines
3.2 KiB
Rust
113 lines
3.2 KiB
Rust
use crate::regs::{RegisterR, RegisterRW};
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use super::slcr;
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#[cfg(feature = "target_zc706")]
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const PS_CLK: u32 = 33_333_333;
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#[cfg(feature = "target_cora_z7_10")]
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const PS_CLK: u32 = 50_000_000;
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enum CpuClockMode {
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/// Clocks run in 4:2:2:1 mode
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C421,
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/// Clocks run in 6:3:2:1 mode
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C621,
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}
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impl CpuClockMode {
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pub fn get() -> Self {
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let regs = slcr::RegisterBlock::new();
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if regs.clk_621_true.read().clk_621_true() {
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CpuClockMode::C621
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} else {
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CpuClockMode::C421
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}
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}
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}
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#[derive(Debug, Clone)]
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pub struct CpuClocks {
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/// ARM PLL: Recommended clock source for the CPUs and the interconnect
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pub arm: u32,
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/// DDR PLL: Recommended clock for the DDR DRAM controller and AXI_HP interfaces
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pub ddr: u32,
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/// I/O PLL: Recommended clock for I/O peripherals
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pub io: u32,
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}
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impl CpuClocks {
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pub fn get() -> Self {
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let regs = slcr::RegisterBlock::new();
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let arm = u32::from(regs.arm_pll_ctrl.read().pll_fdiv()) * PS_CLK;
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let ddr = u32::from(regs.ddr_pll_ctrl.read().pll_fdiv()) * PS_CLK;
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let io = u32::from(regs.io_pll_ctrl.read().pll_fdiv()) * PS_CLK;
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CpuClocks { arm, ddr, io }
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}
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pub fn cpu_6x4x(&self) -> u32 {
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let regs = slcr::RegisterBlock::new();
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let arm_clk_ctrl = regs.arm_clk_ctrl.read();
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let pll = match arm_clk_ctrl.srcsel() {
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slcr::ArmPllSource::ArmPll => self.arm,
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slcr::ArmPllSource::DdrPll => self.ddr,
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slcr::ArmPllSource::IoPll => self.io,
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};
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pll / u32::from(arm_clk_ctrl.divisor())
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}
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pub fn cpu_3x2x(&self) -> u32 {
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self.cpu_6x4x() / 2
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}
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pub fn cpu_2x(&self) -> u32 {
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match CpuClockMode::get() {
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CpuClockMode::C421 =>
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self.cpu_6x4x() / 2,
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CpuClockMode::C621 =>
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self.cpu_6x4x() / 3,
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}
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}
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pub fn cpu_1x(&self) -> u32 {
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match CpuClockMode::get() {
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CpuClockMode::C421 =>
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self.cpu_6x4x() / 4,
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CpuClockMode::C621 =>
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self.cpu_6x4x() / 6,
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}
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}
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pub fn uart_ref_clk(&self) -> u32 {
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let regs = slcr::RegisterBlock::new();
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let uart_clk_ctrl = regs.uart_clk_ctrl.read();
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let pll = match uart_clk_ctrl.srcsel() {
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slcr::PllSource::ArmPll =>
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self.arm,
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slcr::PllSource::DdrPll =>
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self.ddr,
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slcr::PllSource::IoPll =>
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self.io,
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};
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pll / u32::from(uart_clk_ctrl.divisor())
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}
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pub fn enable_ddr(target_clock: u32) {
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let regs = slcr::RegisterBlock::new();
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_reset(true)
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.pll_bypass_force(true)
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);
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let fdiv = (target_clock / PS_CLK).max(127) as u16;
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_reset(false)
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.pll_fdiv(fdiv)
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);
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while ! regs.pll_status.read().ddr_pll_lock() {}
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_bypass_force(false)
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.pll_bypass_qual(false)
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);
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}
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}
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