forked from M-Labs/zynq-rs
177 lines
5.2 KiB
Rust
177 lines
5.2 KiB
Rust
use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_bits_typed};
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#[repr(u8)]
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pub enum DataBusWidth {
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Width32bit = 0b00,
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Width16bit = 0b01,
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}
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#[derive(Debug, Clone, PartialEq)]
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#[repr(u8)]
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pub enum ControllerStatus {
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Init = 0,
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Normal = 1,
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Powerdown = 2,
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SelfRefresh = 3,
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Powerdown1 = 4,
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Powerdown2 = 5,
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Powerdown3 = 6,
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Powerdown4 = 7,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub ddrc_ctrl: DdrcCtrl,
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pub two_rank_cfg: RW<u32>,
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pub hpr_reg: RW<u32>,
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pub lpr_reg: RW<u32>,
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pub wr_reg: RW<u32>,
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pub dram_param_reg0: RW<u32>,
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pub dram_param_reg1: RW<u32>,
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pub dram_param_reg2: RW<u32>,
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pub dram_param_reg3: RW<u32>,
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pub dram_param_reg4: RW<u32>,
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pub dram_init_param: RW<u32>,
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pub dram_emr_reg: RW<u32>,
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pub dram_emr_mr_reg: RW<u32>,
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pub dram_burst8_rdwr: RW<u32>,
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pub dram_disable_dq: RW<u32>,
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pub dram_addr_map_bank: RW<u32>,
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pub dram_addr_map_col: RW<u32>,
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pub dram_addr_map_row: RW<u32>,
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pub dram_odt_reg: RW<u32>,
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pub phy_dbg_reg: RW<u32>,
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pub phy_cmd_timeout_rddata_cpt: RW<u32>,
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pub mode_sts_reg: ModeStsReg,
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pub dll_calib: RW<u32>,
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pub odt_delay_hold: RW<u32>,
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pub ctrl_reg1: RW<u32>,
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pub ctrl_reg2: RW<u32>,
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pub ctrl_reg3: RW<u32>,
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pub ctrl_reg4: RW<u32>,
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_unused0: [RO<u32>; 2],
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pub ctrl_reg5: RW<u32>,
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pub ctrl_reg6: RW<u32>,
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_unused1: [RO<u32>; 8],
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pub che_refresh_timer01: RW<u32>,
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pub che_t_zq: RW<u32>,
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pub che_t_zq_short_interval_reg: RW<u32>,
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pub deep_pwrdwn_reg: RW<u32>,
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pub reg_2c: RW<u32>,
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pub reg_2d: RW<u32>,
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pub dfi_timing: RW<u32>,
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_unused2: [RO<u32>; 2],
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pub che_ecc_control_reg_offset: RW<u32>,
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pub che_corr_ecc_log_reg_offset: RW<u32>,
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pub che_corr_ecc_addr_reg_offset: RW<u32>,
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pub che_corr_ecc_data_31_0_reg_offset: RW<u32>,
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pub che_corr_ecc_data_63_32_reg_offset: RW<u32>,
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pub che_corr_ecc_data_71_64_reg_offset: RW<u32>,
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pub che_uncorr_ecc_log_reg_offset: RW<u32>,
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pub che_uncorr_ecc_addr_reg_offset: RW<u32>,
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pub che_uncorr_ecc_data_31_0_reg_offset: RW<u32>,
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pub che_uncorr_ecc_data_63_32_reg_offset: RW<u32>,
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pub che_uncorr_ecc_data_71_64_reg_offset: RW<u32>,
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pub che_ecc_stats_reg_offset: RW<u32>,
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pub ecc_scrub: RW<u32>,
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pub che_ecc_corr_bit_mask_31_0_reg_offset: RW<u32>,
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pub che_ecc_corr_bit_mask_63_32_reg_offset: RW<u32>,
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_unused3: [RO<u32>; 5],
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pub phy_rcvr_enable: RW<u32>,
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pub phy_config0: RW<u32>,
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pub phy_config1: RW<u32>,
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pub phy_config2: RW<u32>,
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pub phy_config3: RW<u32>,
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_unused4: RO<u32>,
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pub phy_init_ratio0: RW<u32>,
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pub phy_init_ratio1: RW<u32>,
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pub phy_init_ratio2: RW<u32>,
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pub phy_init_ratio3: RW<u32>,
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_unused5: RO<u32>,
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pub phy_rd_dqs_cfg0: RW<u32>,
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pub phy_rd_dqs_cfg1: RW<u32>,
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pub phy_rd_dqs_cfg2: RW<u32>,
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pub phy_rd_dqs_cfg3: RW<u32>,
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_unused6: RO<u32>,
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pub phy_wr_dqs_cfg0: RW<u32>,
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pub phy_wr_dqs_cfg1: RW<u32>,
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pub phy_wr_dqs_cfg2: RW<u32>,
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pub phy_wr_dqs_cfg3: RW<u32>,
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_unused7: RO<u32>,
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pub phy_we_cfg0: RW<u32>,
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pub phy_we_cfg1: RW<u32>,
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pub phy_we_cfg2: RW<u32>,
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pub phy_we_cfg3: RW<u32>,
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_unused8: RO<u32>,
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pub wr_data_slv0: RW<u32>,
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pub wr_data_slv1: RW<u32>,
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pub wr_data_slv2: RW<u32>,
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pub wr_data_slv3: RW<u32>,
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_unused9: RO<u32>,
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pub reg_64: RW<u32>,
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pub reg_65: RW<u32>,
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_unused10: [RO<u32>; 3],
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pub reg69_6a0: RW<u32>,
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pub reg69_6a1: RW<u32>,
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_unused11: RO<u32>,
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pub reg6c_6d2: RW<u32>,
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pub reg6c_6d3: RW<u32>,
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pub reg6e_710: RW<u32>,
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pub reg6e_711: RW<u32>,
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pub reg6e_712: RW<u32>,
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pub reg6e_713: RW<u32>,
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pub phy_dll_sts0: RW<u32>,
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_unused12: RO<u32>,
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pub phy_dll_sts1: RW<u32>,
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pub phy_dll_sts2: RW<u32>,
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pub phy_dll_sts3: RW<u32>,
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_unused13: RO<u32>,
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pub dll_lock_sts: RW<u32>,
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pub phy_ctrl_sts: RW<u32>,
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pub phy_ctrl_sts_reg2: RW<u32>,
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_unused14: [RO<u32>; 5],
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pub axi_id: RW<u32>,
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pub page_mask: RW<u32>,
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pub axi_priority_wr_port0: RW<u32>,
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pub axi_priority_wr_port1: RW<u32>,
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pub axi_priority_wr_port2: RW<u32>,
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pub axi_priority_wr_port3: RW<u32>,
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pub axi_priority_rd_port0: RW<u32>,
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pub axi_priority_rd_port1: RW<u32>,
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pub axi_priority_rd_port2: RW<u32>,
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pub axi_priority_rd_port3: RW<u32>,
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_unused15: [RO<u32>; 27],
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pub excl_access_cfg0: RW<u32>,
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pub excl_access_cfg1: RW<u32>,
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pub excl_access_cfg2: RW<u32>,
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pub excl_access_cfg3: RW<u32>,
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pub mode_reg_read: RW<u32>,
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pub lpddr_ctrl0: RW<u32>,
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pub lpddr_ctrl1: RW<u32>,
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pub lpddr_ctrl2: RW<u32>,
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pub lpddr_ctrl3: RW<u32>,
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}
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impl RegisterBlock {
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pub unsafe fn new() -> &'static mut Self {
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&mut *(0xF8006000 as *mut _)
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}
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}
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register!(ddrc_ctrl, DdrcCtrl, RW, u32);
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register_bit!(ddrc_ctrl,
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/// `false` resets controller, `true` continues
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soft_rstb, 0);
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register_bit!(ddrc_ctrl, powerdown_en, 1);
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register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
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// (ddrc_ctrl) ...
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/// Controller operation mode status
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register!(mode_sts_reg, ModeStsReg, RO, u32);
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register_bits_typed!(mode_sts_reg, operating_mode, u8, ControllerStatus, 0, 2);
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// (mode_sts_reg) ...
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