forked from M-Labs/zynq-rs
406 lines
12 KiB
Rust
406 lines
12 KiB
Rust
#![no_std]
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#![no_main]
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#![feature(asm)]
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#![feature(global_asm)]
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#![feature(naked_functions)]
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#![feature(compiler_builtins_lib)]
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#![feature(never_type)]
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// TODO: disallow unused/dead_code when code moves into a lib crate
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#![allow(dead_code)]
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use core::mem::{uninitialized, transmute};
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use core::ptr::write_volatile;
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use r0::zero_bss;
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use compiler_builtins as _;
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use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
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use smoltcp::time::Instant;
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use smoltcp::socket::SocketSet;
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use mailbox::{MAILBOX_FROM_CORE0, MAILBOX_FROM_CORE1};
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mod regs;
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mod cortex_a9;
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mod clocks;
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mod mailbox;
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mod mpcore;
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mod mutex;
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mod slcr;
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mod uart;
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mod stdio;
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mod eth;
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use crate::cortex_a9::{asm, regs::*, mmu};
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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static mut __stack_start: u32; // refers to the stack for core 0
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static mut __stack1_start: u32; // refers to the stack for core 1
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}
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// program address as u32, for execution after setting up core 1
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static mut START_ADDR_CORE1: u32 = 0;
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// initial stack pointer for starting core 1
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static mut INITIAL_SP_CORE1: u32 = 0; // must be zero (as a flag)
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_MASK: u32 = 0x3;
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match MPIDR.read() & CORE_MASK {
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0 => {
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// executing on core 0
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SP.write(&mut __stack_start as *mut _ as u32);
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boot_core0();
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}
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_ => {
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// executing on core 1 (as there are only cores 0 and 1)
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while INITIAL_SP_CORE1 == 0 {
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// NOTE: This wfe and its loop can be removed as long
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// as the regular boot loader remains in place
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// (i.e. this program is not written into ROM).
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asm::wfe();
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}
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// the following requires a stack (at least later, for the
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// function for setting up the MMU)
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SP.write(INITIAL_SP_CORE1);
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boot_core1();
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}
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}
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}
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#[naked]
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#[inline(never)]
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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// Invalidate SCU, for all cores
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mpcore::RegisterBlock::new().scu_invalidate.write(0xffff);
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zero_bss(&mut __bss_start, &mut __bss_end);
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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// start SCU
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mpcore::RegisterBlock::new().scu_control.modify(
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|_, w| w.enable(true)
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);
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// enable SMP (for starting correct SCU operation)
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ACTLR.modify(|_, w|
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w.smp(true) // SMP mode
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.fw(true) // cache and TLB maintenance broadcast on
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);
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asm::dmb();
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asm::dsb();
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main();
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panic!("return from main");
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});
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}
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#[naked]
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#[inline(never)]
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unsafe fn boot_core1() -> ! {
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l1_cache_init();
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// Invalidate SCU, for core1 only
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mpcore::RegisterBlock::new().scu_invalidate.write(0x00f0);
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// use the MMU L1 Table already set up by core 0
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let mmu_table = mmu::L1Table::get();
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mmu::with_mmu(mmu_table, || {
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// enable SMP (for correct SCU operation)
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ACTLR.modify(|_, w|
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w.smp(true) // SMP mode
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.fw(true) // cache and TLB maintenance broadcast
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);
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asm::dmb();
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asm::dsb();
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// now that the MMU is active using the same table as active
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// on the other core, one can branch to any normal memory
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// location in which the code may reside
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asm!("bx r1" :: "{r1}"(START_ADDR_CORE1) :: "volatile");
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unreachable!();
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});
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}
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fn l1_cache_init() {
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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//
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// Note: Do use dcisw rather than dccisw to only invalidate rather
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// than also clear (which may write values back into the
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// underlying L2 cache or memory!)
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//
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// use the "made-up instruction" (see definition) dciall()
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dciall();
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asm::dsb();
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asm::isb();
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}
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fn stop_core1() {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| {
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w.a9_rst1(true)
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});
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slcr.a9_cpu_rst_ctrl.modify(|_, w| {
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w.a9_clkstop1(true)
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});
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slcr.a9_cpu_rst_ctrl.modify(|_, w| {
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w.a9_rst1(false)
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});
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});
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}
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// Execute f on core 1 using the given stack. Note that these
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// semantics are inherently unsafe as the stack needs to live longer
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// than Rust semantics dictate...hence this method is marked as unsafe
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// to remind the caller to take special care (but also many operations
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// performed would otherwise require `unsafe` blocks).
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unsafe fn run_on_core1(f: fn() -> !, stack: &mut [u32]) {
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// reset and stop core 1 (this is safe to repeat, if the caller
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// has already performed this)
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stop_core1();
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// ensure any mailbox access finishes before the mailbox reset
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asm::dmb();
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// reset the mailbox for sending messages
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MAILBOX_FROM_CORE0.reset_discard();
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MAILBOX_FROM_CORE1.reset_discard();
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// determine address of f and save it as start address for core 1
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write_volatile(
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&mut START_ADDR_CORE1,
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f as *const () as u32
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);
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write_volatile(
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&mut INITIAL_SP_CORE1,
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&mut stack[stack.len() - 1] as *const _ as u32
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);
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// ensure the above is written to cache before it is cleaned
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asm::dmb();
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// TODO: Is the following necessary, considering that the SCU
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// should take care of coherency of all (normal) memory?
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//
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// clean cache lines containing START_ADDR_CORE1 and
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// INITIAL_SP_CORE1
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dccmvac(&START_ADDR_CORE1 as *const _ as u32);
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dccmvac(&INITIAL_SP_CORE1 as *const _ as u32);
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// clean cache lines containing mailboxes
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dccmvac(&MAILBOX_FROM_CORE0 as *const _ as u32);
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dccmvac(&MAILBOX_FROM_CORE1 as *const _ as u32);
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// restart core 1
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| {
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w.a9_rst1(false)
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});
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slcr.a9_cpu_rst_ctrl.modify(|_, w| {
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w.a9_clkstop1(false)
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});
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});
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}
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fn main_core1() -> ! {
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let mut data: [u32; 2] = [42, 42];
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println!("Core 1 SP: 0x{:X}", SP.read());
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loop {
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// effectively perform something similar to `println!("from
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// core 1");` by passing a message to core 0 and having core 0
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// output it via the println! macro
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unsafe {
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println!("sending from core 1");
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MAILBOX_FROM_CORE1.send(&data as *const _ as usize);
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while !MAILBOX_FROM_CORE1.acknowledged() {
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println!("core 1 waiting for acknowledgement from core 0");
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}
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}
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// change data to make it more interesting
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data[1] += 1;
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}
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}
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fn main_core1_program2() -> ! {
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let mut data: [u32; 2] = [4200, 4200];
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println!("Core 1 SP: 0x{:X}", SP.read());
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loop {
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unsafe {
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MAILBOX_FROM_CORE1.send(&data as *const _ as usize);
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while !MAILBOX_FROM_CORE1.acknowledged() {}
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}
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// change data to make it more interesting
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data[0] -= 1;
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data[1] += 1;
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}
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}
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// reserve some memory as stack for core1
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static mut STACK_CORE1: [u32; 256] = [0; 256];
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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fn main() {
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println!("Main.");
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println!("Core 0 SP: 0x{:X}", SP.read());
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let clocks = clocks::CpuClocks::get();
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println!("Clocks: {:?}", clocks);
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println!("CPU speeds: {}/{}/{}/{} MHz",
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clocks.cpu_6x4x() / 1_000_000,
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clocks.cpu_3x2x() / 1_000_000,
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clocks.cpu_2x() / 1_000_000,
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clocks.cpu_1x() / 1_000_000);
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let mut eth = eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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eth.reset_phy();
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// start executing main_core1() on core 1
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unsafe {
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run_on_core1(main_core1, &mut STACK_CORE1[..]);
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}
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println!("Started main_core1() on core 1");
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for _ in 0..5 {
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// wait for data
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while unsafe { !MAILBOX_FROM_CORE1.available() } {}
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// receive data
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let data_ptr = unsafe { MAILBOX_FROM_CORE1.receive() };
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println!(
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"Received via mailbox from core 1: data {} and {} at address 0x{:X}",
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unsafe { (*(data_ptr as *const [u32; 2]))[0] },
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unsafe { (*(data_ptr as *const [u32; 2]))[1] },
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data_ptr
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);
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unsafe {
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MAILBOX_FROM_CORE1.acknowledge(data_ptr);
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}
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}
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stop_core1();
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println!("Stopped core 1.");
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// start executing main_core1_program2() on core 1
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unsafe {
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run_on_core1(main_core1_program2, &mut STACK_CORE1[..]);
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}
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println!("Started main_core1_program2() on core 1");
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for _ in 0..5 {
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// wait for data
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while unsafe { !MAILBOX_FROM_CORE1.available() } {}
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// receive data
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let data_ptr = unsafe { MAILBOX_FROM_CORE1.receive() };
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println!(
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"Received via mailbox from core 1: data {} and {} at address 0x{:X}",
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unsafe { (*(data_ptr as *const [u32; 2]))[0] },
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unsafe { (*(data_ptr as *const [u32; 2]))[1] },
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data_ptr
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);
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unsafe {
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MAILBOX_FROM_CORE1.acknowledge(data_ptr);
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}
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}
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stop_core1();
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println!("Stopped core 1.");
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const RX_LEN: usize = 1;
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let mut rx_descs: [eth::rx::DescEntry; RX_LEN] = unsafe { uninitialized() };
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let mut rx_buffers = [[0u8; eth::MTU]; RX_LEN];
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const TX_LEN: usize = 1;
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let mut tx_descs: [eth::tx::DescEntry; TX_LEN] = unsafe { uninitialized() };
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let mut tx_buffers = [[0u8; eth::MTU]; TX_LEN];
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let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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//let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
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let mut eth = eth.start_tx(
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// HACK
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unsafe { transmute(tx_descs.as_mut()) },
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unsafe { transmute(tx_buffers.as_mut()) },
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);
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let ethernet_addr = EthernetAddress(HWADDR);
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// IP stack
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let local_addr = IpAddress::v4(10, 0, 0, 1);
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
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let mut neighbor_storage = [None; 16];
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let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
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let mut iface = EthernetInterfaceBuilder::new(&mut eth)
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.ethernet_addr(ethernet_addr)
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.ip_addrs(&mut ip_addrs[..])
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.neighbor_cache(neighbor_cache)
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.finalize();
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let mut sockets_storage = [
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None, None, None, None,
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None, None, None, None
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];
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let mut sockets = SocketSet::new(&mut sockets_storage[..]);
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let mut time = 0u32;
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loop {
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time += 1;
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let timestamp = Instant::from_millis(time.into());
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match iface.poll(&mut sockets, timestamp) {
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Ok(_) => {},
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Err(e) => {
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println!("poll error: {}", e);
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}
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}
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// match eth.recv_next() {
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// Ok(Some(pkt)) => {
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// print!("eth: rx {} bytes", pkt.len());
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// for b in pkt.iter() {
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// print!(" {:02X}", b);
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// }
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// println!("");
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// }
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// Ok(None) => {}
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// Err(e) => {
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// println!("eth rx error: {:?}", e);
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// }
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// }
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// match eth.send(512) {
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// Some(mut pkt) => {
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// let mut x = 0;
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// for b in pkt.iter_mut() {
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// *b = x;
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// x += 1;
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// }
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// println!("eth tx {} bytes", pkt.len());
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// }
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// None => println!("eth tx shortage"),
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// }
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}
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}
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#[panic_handler]
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fn panic(info: &core::panic::PanicInfo) -> ! {
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println!("\nPanic: {}", info);
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slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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loop {}
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}
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#[no_mangle]
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pub unsafe extern "C" fn PrefetchAbort() {
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println!("PrefetchAbort");
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loop {}
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}
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#[no_mangle]
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pub unsafe extern "C" fn DataAbort() {
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println!("DataAbort");
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loop {}
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}
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