154 Commits (3496755406f3d9f35b7689c50c0db311c559d7d8)
 

Author SHA1 Message Date
Astro 3496755406 update rust + smoltcp 4 years ago
Astro 959bf8a245 zynq::eth: don't check_link_change if link already established 4 years ago
Astro 4d3b2ac7e5 zynq::ddr: use different data_bus_width for targets
DDR still works only on the zc706, not on the cora z7-10.
4 years ago
Astro cae02947bc zynq::eth: remove all memory barriers
They were not the solution.
4 years ago
Astro afd96bd887 zynq::clocks: unlock slcr in enable_io() 4 years ago
Astro 261455877d zynq::ddr: fix DDR 3x/2x setup, print clocks 4 years ago
Astro ff96bf903b zynq::ddr: only enable_ddr if no clock yet
that's only an issue for the cora z7
4 years ago
Astro d2df5652d0 Revert "zynq: replace unnecessary slcr::unlocked with new"
This reverts commit 6bee1f44f4.
4 years ago
Astro eb56dda44f zynq::slcr::unlocked: fix comment 4 years ago
Sebastien Bourdeauducq 6e50b32e80 openocd: configure SRST for digilent_jtag_smt2_nc + Zynq
Digilent docs say Zynq boards should connect it to GPIO2.

Closes #2
4 years ago
Astro 74c43b3477 zynq::eth::tx: clear entry.word1 for each packet 4 years ago
Astro 99a00e019b zynq::eth: implement phy::extended_status, set clock for link speed 4 years ago
Astro 961e2e1dd0 zynq::{ddr, eth}: fix clock divisor calculation
off-by-one, didn't change behavior.
4 years ago
Astro 04e816d99e zynq::slcr: fix a bitfield index
that didn't solve our problems.
4 years ago
Astro 6bee1f44f4 zynq: replace unnecessary slcr::unlocked with new 4 years ago
Astro 54e4b9281f main: rewrap linked_list_allocator 4 years ago
Astro f688eb83ab default.nix: update cargoSha256 4 years ago
Astro 5c62716a99 zynq::eth: switch rx and tx descriptor words to vcell
vcell can be initialized cleanly.
4 years ago
Astro 1f728686ff rm ram, add linked_list_allocator on ddr 4 years ago
Astro e248d3d3b1 zynq::ddr: optimize memtest 4 years ago
Astro 91bab76ab6 zynq::ddr: fix usable ram size 4 years ago
Astro 43501003f9 openocd/zc706: decimate `adapter_khz` for reliability 4 years ago
Astro ceeaa6427e zynq::ddr: fix typo 4 years ago
Astro 7cdf6c0918 start implementation of a StaticAllocator 4 years ago
Astro fc39885d3b zynq::ddr: fix clock setup 4 years ago
Astro f199ac68b4 zynq::ddr: don't overwrite slcr.ddr_pll_ctrl 4 years ago
Astro 637bb35f43 zynq::ddr: fix memtest progress calculation 4 years ago
Astro 85bd506132 zynq::ddr: parameters 4 years ago
Astro 27114aec62 zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage
this seems to make DDR RAM work.
4 years ago
Astro 9b4f07f37c zynq::ddr, main: parameters, memtest 4 years ago
Astro e61d1268ac zynq::slcr: doc, fix 4 years ago
Astro a4d3360a70 zynq::slcr: implement Display for PllStatus 4 years ago
Astro 838434cdec zynq::ddr: wait for init 4 years ago
Astro 4cf5283ba8 zynq::ddr: implement reset_ddrc(), add to main 4 years ago
Astro a8886de067 zynq::ddr: implement configure_iob() 4 years ago
Astro afda48e3fe zynq::ddr: add clock_setup(), calibrate_iob_impedance() 4 years ago
Astro c046bbf8a2 move slcr, clocks, uart, eth into src/zynq/ 4 years ago
Astro 9d725bcf0f zynq::ddr: init with clock setup 4 years ago
Astro 58cf9833cc slcr: implement PllCfg and DdrClkCtrl 4 years ago
Astro 83b8bb096a add zynq::axi_gp 4 years ago
Astro b541160f38 add zynq::axi_hp 4 years ago
Björn Stein 1804c4c6e8 cortex_a9: add proper L1 cache invalidation 4 years ago
Björn Stein d87b874b21 eth: add memory barriers, reorder access 4 years ago
Björn Stein 9053166acc eth: increase desc list safety 4 years ago
Astro 4e9c38527e rm debug, delint 4 years ago
Astro a76214cb9d eth: split into Eth and EthInner 4 years ago
Astro 0f6bc68d1f eth: prepare link change detection 4 years ago
Astro 378755a0ce main: bump RX_LEN/TX_LEN to 2 4 years ago
Astro 644cc64524 eth: align DescEntries 4 years ago
Astro f9cc561144 link.x: fix __stack_start
This fixes the memory corruption problem.
4 years ago