From cf1983e543ad2c3761da6b05d532ea2587f5e08c Mon Sep 17 00:00:00 2001 From: Astro Date: Tue, 17 Dec 2019 23:35:58 +0100 Subject: [PATCH] split into lib{register, cortex_a9, board_zynq, board_zc706} crates --- Cargo.lock | 59 +++++++++++++++---- Cargo.toml | 25 +------- default.nix | 2 +- libboard_zc706/Cargo.toml | 23 ++++++++ {src => libboard_zc706/src}/abort.rs | 2 +- {src => libboard_zc706/src}/boot.rs | 12 ++-- {src => libboard_zc706/src}/main.rs | 18 +++--- {src => libboard_zc706/src}/main.rs.orig | 0 {src => libboard_zc706/src}/panic.rs | 4 +- {src => libboard_zc706/src}/ram.rs | 4 +- libboard_zynq/Cargo.toml | 25 ++++++++ {src/zynq => libboard_zynq/src}/axi_gp.rs | 0 {src/zynq => libboard_zynq/src}/axi_hp.rs | 2 +- {src/zynq => libboard_zynq/src}/clocks.rs | 2 +- {src/zynq => libboard_zynq/src}/ddr/mod.rs | 2 +- {src/zynq => libboard_zynq/src}/ddr/regs.rs | 3 +- {src/zynq => libboard_zynq/src}/eth/mod.rs | 2 +- .../src}/eth/phy/control.rs | 0 .../src}/eth/phy/extended_status.rs | 0 {src/zynq => libboard_zynq/src}/eth/phy/id.rs | 0 .../zynq => libboard_zynq/src}/eth/phy/mod.rs | 0 .../src}/eth/phy/status.rs | 0 {src/zynq => libboard_zynq/src}/eth/regs.rs | 2 +- {src/zynq => libboard_zynq/src}/eth/rx.rs | 3 +- {src/zynq => libboard_zynq/src}/eth/tx.rs | 3 +- .../zynq => libboard_zynq/src}/flash/bytes.rs | 0 {src/zynq => libboard_zynq/src}/flash/mod.rs | 2 +- {src/zynq => libboard_zynq/src}/flash/regs.rs | 2 +- .../src}/flash/spi_flash_register.rs | 1 + .../src}/flash/transfer.rs | 2 +- src/zynq/mod.rs => libboard_zynq/src/lib.rs | 3 + {src/zynq => libboard_zynq/src}/mpcore.rs | 6 +- {src/zynq => libboard_zynq/src}/slcr.rs | 8 ++- {src => libboard_zynq/src}/stdio.rs | 8 +-- .../src}/uart/baud_rate_gen.rs | 2 +- {src/zynq => libboard_zynq/src}/uart/mod.rs | 2 +- {src/zynq => libboard_zynq/src}/uart/regs.rs | 8 ++- libcortex_a9/Cargo.toml | 23 ++++++++ {src/cortex_a9 => libcortex_a9/src}/asm.rs | 0 {src/cortex_a9 => libcortex_a9/src}/cache.rs | 0 .../src}/exceptions.s | 0 .../mod.rs => libcortex_a9/src/lib.rs | 4 ++ {src/cortex_a9 => libcortex_a9/src}/mmu.rs | 2 +- {src/cortex_a9 => libcortex_a9/src}/mutex.rs | 0 {src/cortex_a9 => libcortex_a9/src}/regs.rs | 6 +- libregister/Cargo.toml | 10 ++++ src/regs.rs => libregister/src/lib.rs | 41 ++++++------- 47 files changed, 218 insertions(+), 105 deletions(-) create mode 100644 libboard_zc706/Cargo.toml rename {src => libboard_zc706/src}/abort.rs (87%) rename {src => libboard_zc706/src}/boot.rs (94%) rename {src => libboard_zc706/src}/main.rs (95%) rename {src => libboard_zc706/src}/main.rs.orig (100%) rename {src => libboard_zc706/src}/panic.rs (79%) rename {src => libboard_zc706/src}/ram.rs (93%) create mode 100644 libboard_zynq/Cargo.toml rename {src/zynq => libboard_zynq/src}/axi_gp.rs (100%) rename {src/zynq => libboard_zynq/src}/axi_hp.rs (96%) rename {src/zynq => libboard_zynq/src}/clocks.rs (99%) rename {src/zynq => libboard_zynq/src}/ddr/mod.rs (99%) rename {src/zynq => libboard_zynq/src}/ddr/regs.rs (98%) rename {src/zynq => libboard_zynq/src}/eth/mod.rs (99%) rename {src/zynq => libboard_zynq/src}/eth/phy/control.rs (100%) rename {src/zynq => libboard_zynq/src}/eth/phy/extended_status.rs (100%) rename {src/zynq => libboard_zynq/src}/eth/phy/id.rs (100%) rename {src/zynq => libboard_zynq/src}/eth/phy/mod.rs (100%) rename {src/zynq => libboard_zynq/src}/eth/phy/status.rs (100%) rename {src/zynq => libboard_zynq/src}/eth/regs.rs (99%) rename {src/zynq => libboard_zynq/src}/eth/rx.rs (97%) rename {src/zynq => libboard_zynq/src}/eth/tx.rs (98%) rename {src/zynq => libboard_zynq/src}/flash/bytes.rs (100%) rename {src/zynq => libboard_zynq/src}/flash/mod.rs (99%) rename {src/zynq => libboard_zynq/src}/flash/regs.rs (98%) rename {src/zynq => libboard_zynq/src}/flash/spi_flash_register.rs (97%) rename {src/zynq => libboard_zynq/src}/flash/transfer.rs (98%) rename src/zynq/mod.rs => libboard_zynq/src/lib.rs (83%) rename {src/zynq => libboard_zynq/src}/mpcore.rs (93%) rename {src/zynq => libboard_zynq/src}/slcr.rs (99%) rename {src => libboard_zynq/src}/stdio.rs (88%) rename {src/zynq => libboard_zynq/src}/uart/baud_rate_gen.rs (98%) rename {src/zynq => libboard_zynq/src}/uart/mod.rs (99%) rename {src/zynq => libboard_zynq/src}/uart/regs.rs (95%) create mode 100644 libcortex_a9/Cargo.toml rename {src/cortex_a9 => libcortex_a9/src}/asm.rs (100%) rename {src/cortex_a9 => libcortex_a9/src}/cache.rs (100%) rename {src/cortex_a9 => libcortex_a9/src}/exceptions.s (100%) rename src/cortex_a9/mod.rs => libcortex_a9/src/lib.rs (63%) rename {src/cortex_a9 => libcortex_a9/src}/mmu.rs (99%) rename {src/cortex_a9 => libcortex_a9/src}/mutex.rs (100%) rename {src/cortex_a9 => libcortex_a9/src}/regs.rs (97%) create mode 100644 libregister/Cargo.toml rename src/regs.rs => libregister/src/lib.rs (84%) diff --git a/Cargo.lock b/Cargo.lock index da258c55..032611d5 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -15,6 +15,53 @@ name = "byteorder" version = "1.3.2" source = "registry+https://github.com/rust-lang/crates.io-index" +[[package]] +name = "libboard_zc706" +version = "0.0.0" +dependencies = [ + "libboard_zynq 0.0.0", + "libcortex_a9 0.0.0", + "libregister 0.0.0", + "linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)", + "r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)", + "smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)", +] + +[[package]] +name = "libboard_zynq" +version = "0.0.0" +dependencies = [ + "bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)", + "libcortex_a9 0.0.0", + "libregister 0.0.0", + "linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)", + "r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)", + "smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)", + "vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)", + "volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + +[[package]] +name = "libcortex_a9" +version = "0.0.0" +dependencies = [ + "bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)", + "libregister 0.0.0", + "r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)", + "smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)", + "vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)", + "volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + +[[package]] +name = "libregister" +version = "0.0.0" +dependencies = [ + "bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)", + "vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)", + "volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "linked_list_allocator" version = "0.6.4" @@ -53,18 +100,6 @@ dependencies = [ "vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)", ] -[[package]] -name = "zc706" -version = "0.0.0" -dependencies = [ - "bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)", - "linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)", - "r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)", - "smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)", - "vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)", - "volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", -] - [metadata] "checksum bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0" "checksum bitflags 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3d155346769a6855b86399e9bc3814ab343cd3d62c7e985113d46a0ec3c281fd" diff --git a/Cargo.toml b/Cargo.toml index 1bd2ccce..4ad039c0 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,8 +1,5 @@ -[package] -name = "zc706" -version = "0.0.0" -authors = ["Astro "] -edition = "2018" +[workspace] +members = ["libregister", "libcortex_a9", "libboard_zynq", "libboard_zc706"] [profile.dev] panic = "abort" @@ -13,21 +10,3 @@ panic = "abort" debug = true lto = true # Link-Time Optimization opt-level = 'z' # Optimize for size. - -[features] -target_zc706 = [] -target_cora_z7_10 = [] -default = ["target_zc706"] - -[dependencies] -r0 = "0.2" -vcell = "0.1" -volatile-register = "0.2" -bit_field = "0.10" -linked_list_allocator = { version = "0.6", default-features = false } - -[dependencies.smoltcp] -git = "https://github.com/m-labs/smoltcp.git" -rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3" -features = ["ethernet", "proto-ipv4", "socket-tcp"] -default-features = false diff --git a/default.nix b/default.nix index c8d74abe..621a8b1b 100644 --- a/default.nix +++ b/default.nix @@ -43,7 +43,7 @@ let zc706 = xbuildRustPackage { name = "zc706"; src = ./.; - cargoSha256 = "1k7b0bzkzhqggrmgzs7md7rrbid0b59a5l96ppr4rwxnh841vcdk"; + cargoSha256 = "15icqy72dck82czpsqz41yjsdar17vpi15v22j6z0zxhzf517rf7"; nativeBuildInputs = [ gcc ]; diff --git a/libboard_zc706/Cargo.toml b/libboard_zc706/Cargo.toml new file mode 100644 index 00000000..700950a6 --- /dev/null +++ b/libboard_zc706/Cargo.toml @@ -0,0 +1,23 @@ +[package] +name = "libboard_zc706" +version = "0.0.0" +authors = ["Astro "] +edition = "2018" + +[features] +target_zc706 = [] +target_cora_z7_10 = [] +default = ["target_zc706"] + +[dependencies] +r0 = "0.2" +linked_list_allocator = { version = "0.6", default-features = false } +libregister = { path = "../libregister" } +libcortex_a9 = { path = "../libcortex_a9" } +libboard_zynq = { path = "../libboard_zynq" } + +[dependencies.smoltcp] +git = "https://github.com/m-labs/smoltcp.git" +rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3" +features = ["ethernet", "proto-ipv4", "socket-tcp"] +default-features = false diff --git a/src/abort.rs b/libboard_zc706/src/abort.rs similarity index 87% rename from src/abort.rs rename to libboard_zc706/src/abort.rs index f177c5bb..dd0250ce 100644 --- a/src/abort.rs +++ b/libboard_zc706/src/abort.rs @@ -1,4 +1,4 @@ -use crate::println; +use libboard_zynq::println; #[no_mangle] pub unsafe extern "C" fn PrefetchAbort() { diff --git a/src/boot.rs b/libboard_zc706/src/boot.rs similarity index 94% rename from src/boot.rs rename to libboard_zc706/src/boot.rs index 08b8e176..d5c362f4 100644 --- a/src/boot.rs +++ b/libboard_zc706/src/boot.rs @@ -1,8 +1,10 @@ use r0::zero_bss; -use vcell::VolatileCell; -use crate::regs::{RegisterR, RegisterW, RegisterRW}; -use crate::cortex_a9::{asm, regs::*, cache, mmu}; -use crate::zynq::{slcr, mpcore}; +use libregister::{ + VolatileCell, + RegisterR, RegisterW, RegisterRW, +}; +use libcortex_a9::{asm, regs::*, cache, mmu}; +use libboard_zynq::{slcr, mpcore}; extern "C" { static mut __bss_start: u32; @@ -81,7 +83,7 @@ unsafe fn boot_core1() -> ! { } fn l1_cache_init() { - use crate::cortex_a9::cache::*; + use libcortex_a9::cache::*; // Invalidate TLBs tlbiall(); diff --git a/src/main.rs b/libboard_zc706/src/main.rs similarity index 95% rename from src/main.rs rename to libboard_zc706/src/main.rs index 896cd609..4b8cd0bc 100644 --- a/src/main.rs +++ b/libboard_zc706/src/main.rs @@ -1,9 +1,6 @@ #![no_std] #![no_main] -#![feature(asm)] -#![feature(global_asm)] #![feature(naked_functions)] -#![feature(never_type)] #![feature(alloc_error_handler)] #![feature(panic_info_message)] // TODO: disallow unused/dead_code when code moves into a lib crate @@ -18,16 +15,13 @@ use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder}; use smoltcp::time::Instant; use smoltcp::socket::SocketSet; use smoltcp::socket::{TcpSocket, TcpSocketBuffer}; +use libboard_zynq::{print, println, self as zynq}; mod boot; -mod regs; -mod cortex_a9; mod abort; mod panic; -mod zynq; -mod stdio; mod ram; -use cortex_a9::mutex::Mutex; +use libcortex_a9::mutex::Mutex; const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef]; @@ -36,8 +30,10 @@ static mut STACK_CORE1: [u32; 512] = [0; 512]; pub fn main() { // zynq::clocks::CpuClocks::enable_io(1_250_000_000); println!("\nzc706 main"); - use regs::RegisterR; - println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins()); + { + use libregister::RegisterR; + println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins()); + } let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode(); let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) }; @@ -110,7 +106,7 @@ pub fn main() { core1.stop(); - cortex_a9::asm::dsb(); + libcortex_a9::asm::dsb(); print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32); for w in core1.stack { print!(" {:08X}", w); diff --git a/src/main.rs.orig b/libboard_zc706/src/main.rs.orig similarity index 100% rename from src/main.rs.orig rename to libboard_zc706/src/main.rs.orig diff --git a/src/panic.rs b/libboard_zc706/src/panic.rs similarity index 79% rename from src/panic.rs rename to libboard_zc706/src/panic.rs index f8e3493e..3beb487c 100644 --- a/src/panic.rs +++ b/libboard_zc706/src/panic.rs @@ -1,4 +1,4 @@ -use crate::{print, println, zynq}; +use libboard_zynq::{slcr, print, println}; #[panic_handler] fn panic(info: &core::panic::PanicInfo) -> ! { @@ -14,6 +14,6 @@ fn panic(info: &core::panic::PanicInfo) -> ! { println!(""); } - zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset()); + slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset()); loop {} } diff --git a/src/ram.rs b/libboard_zc706/src/ram.rs similarity index 93% rename from src/ram.rs rename to libboard_zc706/src/ram.rs index e03e52ad..5ff4970d 100644 --- a/src/ram.rs +++ b/libboard_zc706/src/ram.rs @@ -2,8 +2,8 @@ use core::alloc::GlobalAlloc; use core::ptr::NonNull; use alloc::alloc::Layout; use linked_list_allocator::Heap; -use crate::cortex_a9::mutex::Mutex; -use crate::zynq::ddr::DdrRam; +use libcortex_a9::mutex::Mutex; +use libboard_zynq::ddr::DdrRam; #[global_allocator] static ALLOCATOR: CortexA9Alloc = CortexA9Alloc(Mutex::new(Heap::empty())); diff --git a/libboard_zynq/Cargo.toml b/libboard_zynq/Cargo.toml new file mode 100644 index 00000000..1b0d93a0 --- /dev/null +++ b/libboard_zynq/Cargo.toml @@ -0,0 +1,25 @@ +[package] +name = "libboard_zynq" +version = "0.0.0" +authors = ["Astro "] +edition = "2018" + +[features] +target_zc706 = [] +target_cora_z7_10 = [] +default = ["target_zc706"] + +[dependencies] +r0 = "0.2" +vcell = "0.1" +volatile-register = "0.2" +bit_field = "0.10" +linked_list_allocator = { version = "0.6", default-features = false } +libregister = { path = "../libregister" } +libcortex_a9 = { path = "../libcortex_a9" } + +[dependencies.smoltcp] +git = "https://github.com/m-labs/smoltcp.git" +rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3" +features = ["ethernet", "proto-ipv4", "socket-tcp"] +default-features = false diff --git a/src/zynq/axi_gp.rs b/libboard_zynq/src/axi_gp.rs similarity index 100% rename from src/zynq/axi_gp.rs rename to libboard_zynq/src/axi_gp.rs diff --git a/src/zynq/axi_hp.rs b/libboard_zynq/src/axi_hp.rs similarity index 96% rename from src/zynq/axi_hp.rs rename to libboard_zynq/src/axi_hp.rs index 90951a81..ade5f0c7 100644 --- a/src/zynq/axi_hp.rs +++ b/libboard_zynq/src/axi_hp.rs @@ -2,7 +2,7 @@ use volatile_register::RW; -use crate::{register, register_bit, register_bits}; +use libregister::{register, register_bit, register_bits}; pub unsafe fn axi_hp0() -> &'static RegisterBlock { &*(0xF8008000 as *const _) diff --git a/src/zynq/clocks.rs b/libboard_zynq/src/clocks.rs similarity index 99% rename from src/zynq/clocks.rs rename to libboard_zynq/src/clocks.rs index 42cc895b..810fbe09 100644 --- a/src/zynq/clocks.rs +++ b/libboard_zynq/src/clocks.rs @@ -1,4 +1,4 @@ -use crate::regs::{RegisterR, RegisterW, RegisterRW}; +use libregister::{RegisterR, RegisterW, RegisterRW}; use super::slcr; #[cfg(feature = "target_zc706")] diff --git a/src/zynq/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs similarity index 99% rename from src/zynq/ddr/mod.rs rename to libboard_zynq/src/ddr/mod.rs index 654a3dcc..f91b0d7c 100644 --- a/src/zynq/ddr/mod.rs +++ b/libboard_zynq/src/ddr/mod.rs @@ -1,4 +1,4 @@ -use crate::regs::{RegisterR, RegisterW, RegisterRW}; +use libregister::{RegisterR, RegisterW, RegisterRW}; use crate::{print, println}; use super::slcr; use super::clocks::CpuClocks; diff --git a/src/zynq/ddr/regs.rs b/libboard_zynq/src/ddr/regs.rs similarity index 98% rename from src/zynq/ddr/regs.rs rename to libboard_zynq/src/ddr/regs.rs index eb9da227..1ca54fcb 100644 --- a/src/zynq/ddr/regs.rs +++ b/libboard_zynq/src/ddr/regs.rs @@ -1,7 +1,8 @@ use volatile_register::{RO, RW}; -use crate::{register, register_bit, register_bits_typed}; +use libregister::{register, register_bit, register_bits_typed}; +#[allow(unused)] #[repr(u8)] pub enum DataBusWidth { Width32bit = 0b00, diff --git a/src/zynq/eth/mod.rs b/libboard_zynq/src/eth/mod.rs similarity index 99% rename from src/zynq/eth/mod.rs rename to libboard_zynq/src/eth/mod.rs index 71d370a6..ceb227ed 100644 --- a/src/zynq/eth/mod.rs +++ b/libboard_zynq/src/eth/mod.rs @@ -1,4 +1,4 @@ -use crate::regs::*; +use libregister::*; use crate::println; use super::slcr; use super::clocks::CpuClocks; diff --git a/src/zynq/eth/phy/control.rs b/libboard_zynq/src/eth/phy/control.rs similarity index 100% rename from src/zynq/eth/phy/control.rs rename to libboard_zynq/src/eth/phy/control.rs diff --git a/src/zynq/eth/phy/extended_status.rs b/libboard_zynq/src/eth/phy/extended_status.rs similarity index 100% rename from src/zynq/eth/phy/extended_status.rs rename to libboard_zynq/src/eth/phy/extended_status.rs diff --git a/src/zynq/eth/phy/id.rs b/libboard_zynq/src/eth/phy/id.rs similarity index 100% rename from src/zynq/eth/phy/id.rs rename to libboard_zynq/src/eth/phy/id.rs diff --git a/src/zynq/eth/phy/mod.rs b/libboard_zynq/src/eth/phy/mod.rs similarity index 100% rename from src/zynq/eth/phy/mod.rs rename to libboard_zynq/src/eth/phy/mod.rs diff --git a/src/zynq/eth/phy/status.rs b/libboard_zynq/src/eth/phy/status.rs similarity index 100% rename from src/zynq/eth/phy/status.rs rename to libboard_zynq/src/eth/phy/status.rs diff --git a/src/zynq/eth/regs.rs b/libboard_zynq/src/eth/regs.rs similarity index 99% rename from src/zynq/eth/regs.rs rename to libboard_zynq/src/eth/regs.rs index 4a75f203..b3081be8 100644 --- a/src/zynq/eth/regs.rs +++ b/libboard_zynq/src/eth/regs.rs @@ -1,6 +1,6 @@ use volatile_register::{RO, WO, RW}; -use crate::{register, register_bit, register_bits, register_bits_typed}; +use libregister::{register, register_bit, register_bits, register_bits_typed}; #[repr(C)] pub struct RegisterBlock { diff --git a/src/zynq/eth/rx.rs b/libboard_zynq/src/eth/rx.rs similarity index 97% rename from src/zynq/eth/rx.rs rename to libboard_zynq/src/eth/rx.rs index 7f32fe49..61cf9964 100644 --- a/src/zynq/eth/rx.rs +++ b/libboard_zynq/src/eth/rx.rs @@ -1,6 +1,5 @@ use core::ops::Deref; -use vcell::VolatileCell; -use crate::{register, register_bit, register_bits, regs::*}; +use libregister::*; use super::MTU; #[derive(Debug)] diff --git a/src/zynq/eth/tx.rs b/libboard_zynq/src/eth/tx.rs similarity index 98% rename from src/zynq/eth/tx.rs rename to libboard_zynq/src/eth/tx.rs index 26d3b5b3..a9ae46f8 100644 --- a/src/zynq/eth/tx.rs +++ b/libboard_zynq/src/eth/tx.rs @@ -1,6 +1,5 @@ use core::ops::{Deref, DerefMut}; -use vcell::VolatileCell; -use crate::{register, register_bit, register_bits, regs::*}; +use libregister::*; use super::{MTU, regs}; /// Descriptor entry diff --git a/src/zynq/flash/bytes.rs b/libboard_zynq/src/flash/bytes.rs similarity index 100% rename from src/zynq/flash/bytes.rs rename to libboard_zynq/src/flash/bytes.rs diff --git a/src/zynq/flash/mod.rs b/libboard_zynq/src/flash/mod.rs similarity index 99% rename from src/zynq/flash/mod.rs rename to libboard_zynq/src/flash/mod.rs index f93cdfe9..9909a26f 100644 --- a/src/zynq/flash/mod.rs +++ b/libboard_zynq/src/flash/mod.rs @@ -2,7 +2,7 @@ use crate::{print, println}; use core::marker::PhantomData; -use crate::regs::{RegisterR, RegisterW, RegisterRW}; +use libregister::{RegisterR, RegisterW, RegisterRW}; use super::slcr; use super::clocks::CpuClocks; diff --git a/src/zynq/flash/regs.rs b/libboard_zynq/src/flash/regs.rs similarity index 98% rename from src/zynq/flash/regs.rs rename to libboard_zynq/src/flash/regs.rs index bc1f0d95..a62d8116 100644 --- a/src/zynq/flash/regs.rs +++ b/libboard_zynq/src/flash/regs.rs @@ -1,6 +1,6 @@ use volatile_register::{RO, WO, RW}; -use crate::{register, register_bit, register_bits}; +use libregister::{register, register_bit, register_bits}; #[repr(C)] pub struct RegisterBlock { diff --git a/src/zynq/flash/spi_flash_register.rs b/libboard_zynq/src/flash/spi_flash_register.rs similarity index 97% rename from src/zynq/flash/spi_flash_register.rs rename to libboard_zynq/src/flash/spi_flash_register.rs index 2ad40bb7..ad3521e3 100644 --- a/src/zynq/flash/spi_flash_register.rs +++ b/libboard_zynq/src/flash/spi_flash_register.rs @@ -26,6 +26,7 @@ macro_rules! u8_register { } impl $name { + #[allow(unused)] pub fn is_zeroed(&self) -> bool { self.inner == 0 } diff --git a/src/zynq/flash/transfer.rs b/libboard_zynq/src/flash/transfer.rs similarity index 98% rename from src/zynq/flash/transfer.rs rename to libboard_zynq/src/flash/transfer.rs index 0889f85f..6d761a8f 100644 --- a/src/zynq/flash/transfer.rs +++ b/libboard_zynq/src/flash/transfer.rs @@ -1,4 +1,4 @@ -use crate::regs::{RegisterR, RegisterW, RegisterRW}; +use libregister::{RegisterR, RegisterW, RegisterRW}; use super::regs; use super::{SpiWord, Flash, Manual}; diff --git a/src/zynq/mod.rs b/libboard_zynq/src/lib.rs similarity index 83% rename from src/zynq/mod.rs rename to libboard_zynq/src/lib.rs index 0d72644d..ccfbdb4e 100644 --- a/src/zynq/mod.rs +++ b/libboard_zynq/src/lib.rs @@ -1,6 +1,9 @@ +#![no_std] + pub mod slcr; pub mod clocks; pub mod uart; +pub mod stdio; pub mod eth; pub mod axi_hp; pub mod axi_gp; diff --git a/src/zynq/mpcore.rs b/libboard_zynq/src/mpcore.rs similarity index 93% rename from src/zynq/mpcore.rs rename to libboard_zynq/src/mpcore.rs index bb3b3dab..7e974c23 100644 --- a/src/zynq/mpcore.rs +++ b/libboard_zynq/src/mpcore.rs @@ -1,8 +1,10 @@ ///! Register definitions for Application Processing Unit (mpcore) use volatile_register::{RO, RW}; -use crate::{register, register_at, register_bit, register_bits, - regs::RegisterW, regs::RegisterRW}; +use libregister::{ + register, register_at, register_bit, register_bits, + RegisterW, RegisterRW, +}; #[repr(C)] pub struct RegisterBlock { diff --git a/src/zynq/slcr.rs b/libboard_zynq/src/slcr.rs similarity index 99% rename from src/zynq/slcr.rs rename to libboard_zynq/src/slcr.rs index f372b6e2..54deb53d 100644 --- a/src/zynq/slcr.rs +++ b/libboard_zynq/src/slcr.rs @@ -1,9 +1,11 @@ ///! Register definitions for System Level Control use volatile_register::{RO, RW}; -use crate::{register, register_at, - register_bit, register_bits, register_bits_typed, - regs::RegisterW, regs::RegisterRW}; +use libregister::{ + register, register_at, + register_bit, register_bits, register_bits_typed, + RegisterW, RegisterRW, +}; #[repr(u8)] pub enum PllSource { diff --git a/src/stdio.rs b/libboard_zynq/src/stdio.rs similarity index 88% rename from src/stdio.rs rename to libboard_zynq/src/stdio.rs index 1b771756..d4db7db1 100644 --- a/src/stdio.rs +++ b/libboard_zynq/src/stdio.rs @@ -1,6 +1,6 @@ use core::ops::{Deref, DerefMut}; -use crate::cortex_a9::mutex::{Mutex, MutexGuard}; -use crate::zynq::uart::Uart; +use libcortex_a9::mutex::{Mutex, MutexGuard}; +use crate::uart::Uart; const UART_RATE: u32 = 115_200; static mut UART: Mutex = Mutex::new(LazyUart::Uninitialized); @@ -47,7 +47,7 @@ impl DerefMut for LazyUart { macro_rules! print { ($($arg:tt)*) => ({ use core::fmt::Write; - let mut uart = crate::stdio::get_uart(); + let mut uart = $crate::stdio::get_uart(); let _ = write!(uart, $($arg)*); }) } @@ -56,7 +56,7 @@ macro_rules! print { macro_rules! println { ($($arg:tt)*) => ({ use core::fmt::Write; - let mut uart = crate::stdio::get_uart(); + let mut uart = $crate::stdio::get_uart(); let _ = write!(uart, $($arg)*); let _ = write!(uart, "\r\n"); while !uart.tx_fifo_empty() {} diff --git a/src/zynq/uart/baud_rate_gen.rs b/libboard_zynq/src/uart/baud_rate_gen.rs similarity index 98% rename from src/zynq/uart/baud_rate_gen.rs rename to libboard_zynq/src/uart/baud_rate_gen.rs index 6ee2801e..7c9f0e7f 100644 --- a/src/zynq/uart/baud_rate_gen.rs +++ b/libboard_zynq/src/uart/baud_rate_gen.rs @@ -1,4 +1,4 @@ -use crate::regs::*; +use libregister::*; use super::regs::{RegisterBlock, BaudRateGen, BaudRateDiv}; const BDIV_MIN: u32 = 4; diff --git a/src/zynq/uart/mod.rs b/libboard_zynq/src/uart/mod.rs similarity index 99% rename from src/zynq/uart/mod.rs rename to libboard_zynq/src/uart/mod.rs index 973cb48d..a642ab8a 100644 --- a/src/zynq/uart/mod.rs +++ b/libboard_zynq/src/uart/mod.rs @@ -1,6 +1,6 @@ use core::fmt; -use crate::regs::*; +use libregister::*; use super::slcr; use super::clocks::CpuClocks; diff --git a/src/zynq/uart/regs.rs b/libboard_zynq/src/uart/regs.rs similarity index 95% rename from src/zynq/uart/regs.rs rename to libboard_zynq/src/uart/regs.rs index b2f1e755..e4c60a71 100644 --- a/src/zynq/uart/regs.rs +++ b/libboard_zynq/src/uart/regs.rs @@ -1,7 +1,11 @@ use volatile_register::{RO, WO, RW}; -use crate::{register, register_bit, register_bits, register_bits_typed, register_at}; +use libregister::{ + register, register_at, + register_bit, register_bits, register_bits_typed, +}; +#[allow(unused)] #[repr(u8)] pub enum ChannelMode { Normal = 0b00, @@ -10,6 +14,7 @@ pub enum ChannelMode { RemoteLoopback = 0b11, } +#[allow(unused)] #[repr(u8)] pub enum ParityMode { EvenParity = 0b000, @@ -19,6 +24,7 @@ pub enum ParityMode { None = 0b100, } +#[allow(unused)] #[repr(u8)] pub enum StopBits { One = 0b00, diff --git a/libcortex_a9/Cargo.toml b/libcortex_a9/Cargo.toml new file mode 100644 index 00000000..c4bdcd70 --- /dev/null +++ b/libcortex_a9/Cargo.toml @@ -0,0 +1,23 @@ +[package] +name = "libcortex_a9" +version = "0.0.0" +authors = ["Astro "] +edition = "2018" + +[features] +target_zc706 = [] +target_cora_z7_10 = [] +default = ["target_zc706"] + +[dependencies] +r0 = "0.2" +vcell = "0.1" +volatile-register = "0.2" +bit_field = "0.10" +libregister = { path = "../libregister" } + +[dependencies.smoltcp] +git = "https://github.com/m-labs/smoltcp.git" +rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3" +features = ["ethernet", "proto-ipv4", "socket-tcp"] +default-features = false diff --git a/src/cortex_a9/asm.rs b/libcortex_a9/src/asm.rs similarity index 100% rename from src/cortex_a9/asm.rs rename to libcortex_a9/src/asm.rs diff --git a/src/cortex_a9/cache.rs b/libcortex_a9/src/cache.rs similarity index 100% rename from src/cortex_a9/cache.rs rename to libcortex_a9/src/cache.rs diff --git a/src/cortex_a9/exceptions.s b/libcortex_a9/src/exceptions.s similarity index 100% rename from src/cortex_a9/exceptions.s rename to libcortex_a9/src/exceptions.s diff --git a/src/cortex_a9/mod.rs b/libcortex_a9/src/lib.rs similarity index 63% rename from src/cortex_a9/mod.rs rename to libcortex_a9/src/lib.rs index f7d839f0..15bca232 100644 --- a/src/cortex_a9/mod.rs +++ b/libcortex_a9/src/lib.rs @@ -1,3 +1,7 @@ +#![no_std] +#![feature(asm, global_asm)] +#![feature(never_type)] + pub mod asm; pub mod regs; pub mod cache; diff --git a/src/cortex_a9/mmu.rs b/libcortex_a9/src/mmu.rs similarity index 99% rename from src/cortex_a9/mmu.rs rename to libcortex_a9/src/mmu.rs index 9890b12e..4cbb9c1e 100644 --- a/src/cortex_a9/mmu.rs +++ b/libcortex_a9/src/mmu.rs @@ -1,6 +1,6 @@ use bit_field::BitField; use super::{regs::*, asm}; -use crate::regs::RegisterW; +use libregister::RegisterW; #[derive(Copy, Clone)] #[repr(u8)] diff --git a/src/cortex_a9/mutex.rs b/libcortex_a9/src/mutex.rs similarity index 100% rename from src/cortex_a9/mutex.rs rename to libcortex_a9/src/mutex.rs diff --git a/src/cortex_a9/regs.rs b/libcortex_a9/src/regs.rs similarity index 97% rename from src/cortex_a9/regs.rs rename to libcortex_a9/src/regs.rs index d4141b8e..8f892419 100644 --- a/src/cortex_a9/regs.rs +++ b/libcortex_a9/src/regs.rs @@ -1,5 +1,7 @@ -use crate::{register_bit, register_bits}; -use crate::regs::{RegisterR, RegisterW, RegisterRW}; +use libregister::{ + register_bit, register_bits, + RegisterR, RegisterW, RegisterRW, +}; macro_rules! def_reg_r { ($name:tt, $type: ty, $asm_instr:tt) => { diff --git a/libregister/Cargo.toml b/libregister/Cargo.toml new file mode 100644 index 00000000..e0855569 --- /dev/null +++ b/libregister/Cargo.toml @@ -0,0 +1,10 @@ +[package] +name = "libregister" +version = "0.0.0" +authors = ["Astro "] +edition = "2018" + +[dependencies] +vcell = "0.1" +volatile-register = "0.2" +bit_field = "0.10" diff --git a/src/regs.rs b/libregister/src/lib.rs similarity index 84% rename from src/regs.rs rename to libregister/src/lib.rs index 760acf91..e4ef1e75 100644 --- a/src/regs.rs +++ b/libregister/src/lib.rs @@ -1,10 +1,11 @@ //! Type-safe interface to peripheral registers akin to the code that //! svd2rust generates. -#![allow(unused)] -use vcell::VolatileCell; -use volatile_register::{RO, WO, RW}; -use bit_field::BitField; +#![no_std] + +pub use vcell::VolatileCell; +pub use volatile_register::{RO, WO, RW}; +pub use bit_field::BitField; /// A readable register pub trait RegisterR { @@ -51,7 +52,7 @@ macro_rules! register_common { #[macro_export] macro_rules! register_r { ($mod_name: ident, $struct_name: ident) => ( - impl crate::regs::RegisterR for $struct_name { + impl libregister::RegisterR for $struct_name { type R = $mod_name::Read; fn read(&self) -> Self::R { @@ -65,7 +66,7 @@ macro_rules! register_r { #[macro_export] macro_rules! register_w { ($mod_name: ident, $struct_name: ident) => ( - impl crate::regs::RegisterW for $struct_name { + impl libregister::RegisterW for $struct_name { type W = $mod_name::Write; fn zeroed() -> $mod_name::Write { @@ -84,7 +85,7 @@ macro_rules! register_w { #[macro_export] macro_rules! register_rw { ($mod_name: ident, $struct_name: ident) => ( - impl crate::regs::RegisterRW for $struct_name { + impl libregister::RegisterRW for $struct_name { fn modify Self::W>(&mut self, f: F) { unsafe { self.inner.modify(|inner| { @@ -101,7 +102,7 @@ macro_rules! register_rw { #[macro_export] macro_rules! register_vcell { ($mod_name: ident, $struct_name: ident) => ( - impl crate::regs::RegisterR for $struct_name { + impl libregister::RegisterR for $struct_name { type R = $mod_name::Read; fn read(&self) -> Self::R { @@ -109,7 +110,7 @@ macro_rules! register_vcell { $mod_name::Read { inner } } } - impl crate::regs::RegisterW for $struct_name { + impl libregister::RegisterW for $struct_name { type W = $mod_name::Write; fn zeroed() -> $mod_name::Write { @@ -120,7 +121,7 @@ macro_rules! register_vcell { self.inner.set(w.inner); } } - impl crate::regs::RegisterRW for $struct_name { + impl libregister::RegisterRW for $struct_name { fn modify Self::W>(&mut self, f: F) { let r = self.read(); let w = $mod_name::Write { inner: r.inner }; @@ -136,28 +137,28 @@ macro_rules! register_vcell { macro_rules! register { // Define read-only register ($mod_name: ident, $struct_name: ident, RO, $inner: ty) => ( - crate::register_common!($mod_name, $struct_name, volatile_register::RO<$inner>, $inner); - crate::register_r!($mod_name, $struct_name); + libregister::register_common!($mod_name, $struct_name, libregister::RO<$inner>, $inner); + libregister::register_r!($mod_name, $struct_name); ); // Define write-only register ($mod_name: ident, $struct_name: ident, WO, $inner: ty) => ( - crate::register_common!($mod_name, $struct_name, volatile_register::WO<$inner>, $inner); - crate::register_w!($mod_name, $struct_name); + libregister::register_common!($mod_name, $struct_name, volatile_register::WO<$inner>, $inner); + libregister::register_w!($mod_name, $struct_name); ); // Define read-write register ($mod_name: ident, $struct_name: ident, RW, $inner: ty) => ( - crate::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner); - crate::register_r!($mod_name, $struct_name); - crate::register_w!($mod_name, $struct_name); - crate::register_rw!($mod_name, $struct_name); + libregister::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner); + libregister::register_r!($mod_name, $struct_name); + libregister::register_w!($mod_name, $struct_name); + libregister::register_rw!($mod_name, $struct_name); ); // Define read-write register ($mod_name: ident, $struct_name: ident, VolatileCell, $inner: ty) => ( - crate::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner); - crate::register_vcell!($mod_name, $struct_name); + libregister::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner); + libregister::register_vcell!($mod_name, $struct_name); ); }