forked from M-Labs/zynq-rs
libcortex_a9/mutex: use AcqRel for CAS operations
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bb09d25378
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c13ca614ef
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@ -3,7 +3,7 @@ use core::sync::atomic::{AtomicU32, Ordering};
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use core::cell::UnsafeCell;
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use core::cell::UnsafeCell;
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use super::{
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use super::{
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spin_lock_yield, notify_spin_lock,
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spin_lock_yield, notify_spin_lock,
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asm::{dmb, enter_critical, exit_critical}
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asm::{enter_critical, exit_critical}
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};
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};
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const LOCKED: u32 = 1;
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const LOCKED: u32 = 1;
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@ -32,30 +32,27 @@ impl<T> Mutex<T> {
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/// Lock the Mutex, blocks when already locked
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/// Lock the Mutex, blocks when already locked
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pub fn lock(&self) -> MutexGuard<T> {
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pub fn lock(&self) -> MutexGuard<T> {
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let mut irq = unsafe { enter_critical() };
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let mut irq = unsafe { enter_critical() };
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while self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::Acquire) != UNLOCKED {
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while self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::AcqRel) != UNLOCKED {
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unsafe {
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unsafe {
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exit_critical(irq);
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exit_critical(irq);
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spin_lock_yield();
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spin_lock_yield();
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irq = enter_critical();
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irq = enter_critical();
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}
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}
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}
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}
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dmb();
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MutexGuard { mutex: self, irq }
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MutexGuard { mutex: self, irq }
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}
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}
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pub fn try_lock(&self) -> Option<MutexGuard<T>> {
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pub fn try_lock(&self) -> Option<MutexGuard<T>> {
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let irq = unsafe { enter_critical() };
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let irq = unsafe { enter_critical() };
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if self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::Acquire) != UNLOCKED {
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if self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::AcqRel) != UNLOCKED {
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unsafe { exit_critical(irq) };
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unsafe { exit_critical(irq) };
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None
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None
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} else {
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} else {
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dmb();
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Some(MutexGuard { mutex: self, irq })
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Some(MutexGuard { mutex: self, irq })
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}
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}
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}
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}
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fn unlock(&self) {
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fn unlock(&self) {
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dmb();
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self.locked.store(UNLOCKED, Ordering::Release);
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self.locked.store(UNLOCKED, Ordering::Release);
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notify_spin_lock();
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notify_spin_lock();
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