From a32d7abb9a8875dab71a5d89a6a28ad5786f6ce7 Mon Sep 17 00:00:00 2001 From: Astro Date: Thu, 19 Nov 2020 19:21:38 +0100 Subject: [PATCH] libboard_zynq: rename ddr DCI_FREQ to DCI_MAX_FREQ --- libboard_zynq/src/ddr/mod.rs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs index f70175f..7d78335 100644 --- a/libboard_zynq/src/ddr/mod.rs +++ b/libboard_zynq/src/ddr/mod.rs @@ -20,8 +20,7 @@ const DDR_FREQ: u32 = 525_000_000; /// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz const DDR_FREQ: u32 = 533_333_333; -/// MT41K256M16HA-125 -const DCI_FREQ: u32 = 10_000_000; +const DCI_MAX_FREQ: u32 = 10_000_000; pub struct DdrRam { regs: &'static mut regs::RegisterBlock, @@ -61,7 +60,7 @@ impl DdrRam { } fn calculate_dci_divisors(clocks: &Clocks) -> (u8, u8) { - let target = (DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ; + let target = (DCI_MAX_FREQ - 1 + clocks.ddr) / DCI_MAX_FREQ; let mut best = None; let mut best_error = 0;