From 4a1d0fc0c3de0e4727b9ad0008cdf1493a9c4887 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bj=C3=B6rn=20Stein?= <bjoern.stein@quantum-factory.de>
Date: Thu, 14 Nov 2019 02:11:58 +0100
Subject: [PATCH] zynq::mpcore: add register definitions

---
 src/zynq/mod.rs    |  1 +
 src/zynq/mpcore.rs | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 src/zynq/mpcore.rs

diff --git a/src/zynq/mod.rs b/src/zynq/mod.rs
index 3cd0723a..d4625d06 100644
--- a/src/zynq/mod.rs
+++ b/src/zynq/mod.rs
@@ -5,3 +5,4 @@ pub mod eth;
 pub mod axi_hp;
 pub mod axi_gp;
 pub mod ddr;
+pub mod mpcore;
diff --git a/src/zynq/mpcore.rs b/src/zynq/mpcore.rs
new file mode 100644
index 00000000..36e503ce
--- /dev/null
+++ b/src/zynq/mpcore.rs
@@ -0,0 +1,29 @@
+///! Register definitions for Application Processing Unit (mpcore)
+
+use volatile_register::{RO, RW, WO};
+use crate::{register, register_at, register_bit};
+
+#[repr(C)]
+pub struct RegisterBlock {
+    pub scu_control: ScuControl,
+    pub scu_config: RO<u32>,
+    pub scu_cpu_power: RW<u32>,
+    pub scu_invalidate: WO<u32>,
+    reserved0: [u32; 12],
+    pub filter_start: RW<u32>,
+    pub filter_end: RW<u32>,
+    reserved1: [u32; 2],
+    pub scu_access_control: RW<u32>,
+    pub scu_non_secure_access_control: RW<u32>,
+    // there is plenty more (unimplemented)
+}
+register_at!(RegisterBlock, 0xF8F00000, new);
+
+register!(scu_control, ScuControl, RW, u32);
+register_bit!(scu_control, ic_standby_enable, 6);
+register_bit!(scu_control, scu_standby_enable, 5);
+register_bit!(scu_control, force_to_port0_enable, 4);
+register_bit!(scu_control, scu_speculative_linefill_enable, 3);
+register_bit!(scu_control, scu_rams_parity_enable, 2);
+register_bit!(scu_control, address_filtering_enable, 1);
+register_bit!(scu_control, enable, 0);