From 2c756ba32eff003bf3808b0287182c48c1730ccc Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Fri, 1 May 2020 01:11:35 +0200
Subject: [PATCH] libcortex_a9: migrate from asm! to llvm_asm! to avoid future
 breakage

---
 libcortex_a9/src/asm.rs   | 12 ++++++------
 libcortex_a9/src/cache.rs | 18 +++++++++---------
 libcortex_a9/src/lib.rs   |  2 +-
 libcortex_a9/src/regs.rs  |  4 ++--
 4 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/libcortex_a9/src/asm.rs b/libcortex_a9/src/asm.rs
index c7a92b2..5c2019b 100644
--- a/libcortex_a9/src/asm.rs
+++ b/libcortex_a9/src/asm.rs
@@ -1,35 +1,35 @@
 /// The classic no-op
 #[inline]
 pub fn nop() {
-    unsafe { asm!("nop" :::: "volatile") }
+    unsafe { llvm_asm!("nop" :::: "volatile") }
 }
 
 /// Wait For Event
 #[inline]
 pub fn wfe() {
-    unsafe { asm!("wfe" :::: "volatile") }
+    unsafe { llvm_asm!("wfe" :::: "volatile") }
 }
 
 /// Send Event
 #[inline]
 pub fn sev() {
-    unsafe { asm!("sev" :::: "volatile") }
+    unsafe { llvm_asm!("sev" :::: "volatile") }
 }
 
 /// Data Memory Barrier
 #[inline]
 pub fn dmb() {
-    unsafe { asm!("dmb" :::: "volatile") }
+    unsafe { llvm_asm!("dmb" :::: "volatile") }
 }
 
 /// Data Synchronization Barrier
 #[inline]
 pub fn dsb() {
-    unsafe { asm!("dsb" :::: "volatile") }
+    unsafe { llvm_asm!("dsb" :::: "volatile") }
 }
 
 /// Instruction Synchronization Barrier
 #[inline]
 pub fn isb() {
-    unsafe { asm!("isb" :::: "volatile") }
+    unsafe { llvm_asm!("isb" :::: "volatile") }
 }
diff --git a/libcortex_a9/src/cache.rs b/libcortex_a9/src/cache.rs
index 346ed6c..f62d88f 100644
--- a/libcortex_a9/src/cache.rs
+++ b/libcortex_a9/src/cache.rs
@@ -2,7 +2,7 @@
 #[inline(always)]
 pub fn tlbiall() {
     unsafe {
-        asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
     }
 }
 
@@ -10,7 +10,7 @@ pub fn tlbiall() {
 #[inline(always)]
 pub fn iciallu() {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
     }
 }
 
@@ -18,7 +18,7 @@ pub fn iciallu() {
 #[inline(always)]
 pub fn bpiall() {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
     }
 }
 
@@ -26,7 +26,7 @@ pub fn bpiall() {
 #[inline(always)]
 pub fn dccsw(setway: u32) {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
     }
 }
 
@@ -38,7 +38,7 @@ pub fn dcisw(setway: u32) {
         // also see example code (for DCCISW, but DCISW will be
         // analogous) "Example code for cache maintenance operations"
         // on pages B2-1286 and B2-1287.
-        asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
     }
 }
 
@@ -58,7 +58,7 @@ pub fn dciall() {
 
     // select L1 data cache
     unsafe {
-        asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
+        llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
     }
 
     // Invalidate entire D-Cache by iterating every set and every way
@@ -101,7 +101,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
 #[inline(always)]
 pub fn dccimvac(addr: usize) {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
     }
 }
 
@@ -122,7 +122,7 @@ pub fn dcci_slice<T>(slice: &mut [T]) {
 #[inline(always)]
 pub fn dccmvac(addr: usize) {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
     }
 }
 
@@ -148,7 +148,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
 /// affecting more data than intended.
 #[inline(always)]
 pub unsafe fn dcimvac(addr: usize) {
-    asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
+    llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
 }
 
 /// Data cache clean and invalidate for an object.
diff --git a/libcortex_a9/src/lib.rs b/libcortex_a9/src/lib.rs
index 8cd9aae..1ac96bb 100644
--- a/libcortex_a9/src/lib.rs
+++ b/libcortex_a9/src/lib.rs
@@ -1,5 +1,5 @@
 #![no_std]
-#![feature(asm, global_asm)]
+#![feature(llvm_asm, global_asm)]
 #![feature(never_type)]
 
 extern crate alloc;
diff --git a/libcortex_a9/src/regs.rs b/libcortex_a9/src/regs.rs
index f3b0977..2d5c261 100644
--- a/libcortex_a9/src/regs.rs
+++ b/libcortex_a9/src/regs.rs
@@ -11,7 +11,7 @@ macro_rules! def_reg_r {
             #[inline]
             fn read(&self) -> Self::R {
                 let mut value: u32;
-                unsafe { asm!($asm_instr : "=r" (value) ::: "volatile") }
+                unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
                 value.into()
             }
         }
@@ -26,7 +26,7 @@ macro_rules! def_reg_w {
             #[inline]
             fn write(&mut self, value: Self::W) {
                 let value: u32 = value.into();
-                unsafe { asm!($asm_instr :: "r" (value) :: "volatile") }
+                unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
             }
 
             #[inline]