Kirdy Revision 0_3 #23

Merged
sb10q merged 1 commits from linuswck/kirdy:rev0_3 into master 2024-08-17 17:37:24 +08:00
Member

Progress

  • Schematics
  • Footprints for new Components used
  • PCB Layout(with rev number updated)
  • Verify and Fill in the Part Numbers for all components
  • Add 3D models to all the headers, switches and physically big components
  • Review for Schematics and PCB Layout
  • Update the Panel (Issue #10)
    - Update PDF Schematics
    - Add scripts to generate production file(Gerber, Drill, Drill Map, Component Placement File, Schematics PDF, Step 3D Model Files)
  • Cleanup files and Add screws P/N
  • Write flake.nix so that the path is setup there instead of inside the Python Scripts
  • Able to generate production files with nix build .
    • BOM, Gerber, Drill, Drill Map, Component Placement File, Schematics PDF, Step 3D Model Files
  • PCB is submitted to be fabricated

Related PR: sinara-hw/kirdyAdapter#1
Related New Repo: https://git.m-labs.hk/linuswck/KiCAD_BOM_Generator

Change Log:

PCB

  • Update the clearance rules and trace width for PCB Manufacturing
    • There is no layout change.
    • min_clearance: 0.088899mm -> 0.09mm
      • Avoid mills to mm conversion error
    • min_copper_edge_clearance: 0.25mm -> 0.3mm
    • min_hole_clearance: 0.199mm -> 0.254mm
    • min_trace_width: 0.08889mm -> 0.09mm

Sch

  • A feedback net for TEC DAC is connected to MCU following sinara-hw Thermostat
    image
  • Add optional 0R pads to bias TEC_VSEN instead of using 3V3 power supply
    image
  • Correct the OpAmp Input Polarity for TEC_VSEN
    • TEC+ should connect to OpAmp IN+
    • TEC- should connect to OpAmp IN-
      image
  • Update P/Ns and comments
  • Place Y169010R0000T9L Precision Power Resistor instead of PDY10R000F and its jumper resistor accordingly
    • Cannot source PDY10R000F Precision Power Resistor
  • Place the 5 Pin 2.54mm Pitch MCU Prog Header and assign P/N
  • Add Screws P/Ns from JLCPCB
  • Add SMA Jack to SMA Plug Cable
    • Mount the Jack to front panel and connect it to LD Adapter modulation input
  • 35V 2u2 PMLCAP is changed to be a 16V version of the same series for lower cost
    • Footprint on PCB is changed accordingly
    • 35MU225MC14532 -> 16MU225MB23225
      image

Front Panel

  • Complete Front Panel Exploded Assembly and Technical Drawings are drawn in FreeCad are added
  • Add Output files for production

Review Major Change:

  • Add LEDs and TestPoints for all Power Rails
    • the most important power rails is still accessible even after LD Adapter is installed
  • Custom Net Clearance Constraints Rules are created for POE_12V and Other Power Nets for safety reason
    • (Kicad 7 new features)
    • 1 mm Clearance is maintained
(version 1)

(rule "PoE PWR Clearance Between GND and PoE AC Input"
	(constraint clearance (min 1.0mm))
	(condition " A.NetClass != B.NetClass && A.NetClass == 'PWR'  && B.NetClass == 'POE_PWR' " ))

- Replace the input capacitors of LT304x LDOs with C0G/ low ESR Tantalum Capacitor

  • Use C0G capacitors along the LD Drive Signal Path
    image

  • Optimize the number of tantalum capacitors for lower cost

    • Replace some of the non-critical power stages with Electrolytic capacitor
      • PoE Output LPF Filter, 12V right after reverse voltage protection stage, 3V3 near Ethernet LNA8742A IC, Digital 12V input
        image
        image
        image

Delete redundant tantalum capacitors or Reposition the tantalum capacitors to the LT304x Input for lower microphonics
- 9V output tantalum capacitors is replaced by multiple 22u ceramics

  • Add TAN Caps to all LT304x SET Pin

    • SET pin connected to the internal Error Amplifier
    • Using TAN Caps can avoid microphonics noise to be amplified
    • Datasheet: CSet Max = 22uF
    • Value is selected with the consideration of physical size constraint and package's ESR
      image
  • Replace the FB at -6V and +15V LDO input with a Pi LC LPF
    image

Front Panel and Ports Alignment

  • Add Front Panel FreeCad Assembly and add the 3D models to the PCB
    • Extend the board edge so that the ports protrude into the front panel
      image
    • Dashed silkscreen is the Front Panel Edge PCB edge
      image
  • Add front panel outline for port alignment (in User1 Layer)
    image
  • Add alternate Footprint LTC6655 Vref IC
    image
    image

  • Add LPF and Buffer for TEC Driver VREF
    image

Kirdy LD Adapter

  • Improve Kirdy LD Adapter 3D Model for checking clearance
    • Total Vertical Mating Height (from Kirdy PCB Top Layer to the Laser Mount) = 11(Stnadoff) +1.6(LD Adapter Board Thickness + 19(Laser Mount Height) = 31.6mm < 35.3mm(max allowed height)
  • Add Wurth Elektronik's solder standoffs
  • Add 2 more mounting holes for Kirdy LD Adapter
    image

MCU Extension Headers

  • Add 12V to the header
    image
  • Add 4 Wurth Elektronik's solder standoffs for the MCU Extension Connectors
  • Kirdy LD Adapter's SMA Connector should not have clearance issue even if the MCU Extension board is installed.
    • SMA Cable requires ~3mm being straight before being able to be bent
      image

Others

  • Add back reference designators on silkscreen for all connectors
    • USB, SMA, Ethernet, MCU EXT HDR, MCU Programming HDRs, Power Jacks, SWs
  • Extract and Add some 3D models from Sinara-hw for some footprints

Major PCB Layout Changes

  • Routing of Mod_IN Signal is routed closer to the edge

    • Max Clearance is maintained between digital signal for MCU EXT HDR to reduce cross talk
      • 22x trace width of Mod_IN
        image

  • Add Via Fencing to Mod_IN Signal
    image

  • 8V LDO circuitry is relocated due to the new mounting hole placement
    image

  • part of then drive stage circuit is repositioned due to the placement of mounting hole

    • Capacitor placements are improved with the signal path is routed in daisy chain connection topology
      image
  • 4.096 Vref IC for the LD Drive DAC is repositioned to create more distance from MCU signals
    image

  • Add at least 1mm clearance between primary and secondary side of PoE
    image

  • Relocate the programming HDRs to a more accessible place
    image

General:

  • Migrate current project from Kicad 6 to Kicad 7
    • Components can be marked DNP instead of marking it by setting a DNP value
  • Correct incorrect MFR_PN and MFR_PN_ALT
    • See Issue #28

Python Scripts to Generate all Production Files

Usage

  • For NixOs User, install kicad in nix profile, run the scripts without setting any flags should generate the productions files.
  • For non-NixOs User, the path to "kicad_netlist_reader.py" scripts and the location of the kicad-builtin 3D models must be specified.
  • Command to run: python -m scripts.generate_production_files.py

Footprint

  • Enlarge the courtyard and silkscreen area for PM1202 so that it can be seated flat on the PCB

Front Panel Design

  • Port the step file outline and dxf markings to Kicad Project

    • Marking texts can be modified via Kicad now
  • Change "fiber" to "laser"

  • Use a custom font Prison Gothic (Light) Font for all the non-logo text markings

    • The font is not included in this repo
    • Font is needed to be installed to the system wide for it to render.
  • Add a production folder storing the production files

Schematics:

Top

  • Correct Temperature DAC SPI Signals Connections
    • See Issue #25 for details
      image
  • Add Front Panel 3D Model and Kirdy LD Adapter 3D model to the board
  • Add Mounting Holes for Kirdy LD Adapter
    • Kirdy LD Adapter has heavy copper thermal mass for laser diode. Extra mounting holes are required to secure the board from coming out.

3D Model Overview:
Top:
image
Front Panel View:
image

DriveStage

  • PD TIA and LPF Stage uses TL082Hx

    • See Issue #19 for details
      image
  • Add alternate precision power resistor for Drive Stage

    • MFR_PN: Y169010R0000T9L from Vishay Precision Group
      image
  • Add a switch to 50Ohm termination to be enabled optionally for modulation signal

    • TERM_IND connects directly to the STM32 pin
    • image

MCU

  • Add REF3033 Vref to MCU ADC Vref

    • To improve the ADC measurement of PD signal through MCU
      image
  • Add 2.54mm pitch redundant programming header

  • Remove Ethernet PoE Reset as the PoE Power supply circuit is changed

    • Note: MCU_Rstn Port was passed to reset Ethernet PoE Power
      image

digital supply

  • Add soft start to 12V Power Jack
    image

  • Use a RJ45 PoE Jack without internal rectifier and connect it directly to PM1202

    • See Issue #24
      image
      image

thermostat

  • Add alternate footprint for ADC

    • AD7172-4BCPZ(QFN32) is added as alternate ADC
    • Use a separated power filtering network for the alternate ADC
      image
  • Change AD5680 DAC output range to 0-2V

    • Follow the output voltage range of Sinara-hw Thermostat v2.2.2
      image
  • Fix wrong TEC polarity

    • See Issue #27
  • Fix wrong TEC Driver Current Sense Resistor MFR_PN

    • See Issue #26

Modifications Observed on the Prototype board

  • Tune the V-I Amplifier Feedback path and LD- Out series RC network
    image

  • Change the output 10Ohm power resistor to PDY10R000F
    image

  • Ethernet Signals are being pulled up now instead of pulling down.
    image

  • Parallel Capacitor at LD DAC Output Resistor

    • See Issue #22
      image
  • Modify the freq comp network of Buck converter to improve stability and transient response

    • See Issue #21
      image

Issues Fixed:

Close #10
Close #14
Close #15
Close #24
Close #25
Close #26
Close #27
Close #28

# Progress - [x] Schematics - [x] Footprints for new Components used - [x] PCB Layout(with rev number updated) - [x] Verify and Fill in the Part Numbers for all components - [x] Add 3D models to all the headers, switches and physically big components - [x] Review for Schematics and PCB Layout - [x] Update the Panel (Issue #10) ~~- [ ] Update PDF Schematics~~ ~~- [ ] Add scripts to generate production file(Gerber, Drill, Drill Map, Component Placement File, Schematics PDF, Step 3D Model Files)~~ - [x] Cleanup files and Add screws P/N - [x] Write flake.nix so that the path is setup there instead of inside the Python Scripts - [x] Able to generate production files with `nix build .` - BOM, Gerber, Drill, Drill Map, Component Placement File, Schematics PDF, Step 3D Model Files - [ ] PCB is submitted to be fabricated Related PR: https://git.m-labs.hk/sinara-hw/kirdyAdapter/pulls/1 Related New Repo: https://git.m-labs.hk/linuswck/KiCAD_BOM_Generator # Change Log: ## Production Related Change: ### PCB - Update the clearance rules and trace width for PCB Manufacturing - There is no layout change. - min_clearance: 0.088899mm -> 0.09mm - Avoid mills to mm conversion error - min_copper_edge_clearance: 0.25mm -> 0.3mm - min_hole_clearance: 0.199mm -> 0.254mm - min_trace_width: 0.08889mm -> 0.09mm ### Sch - A feedback net for TEC DAC is connected to MCU following sinara-hw Thermostat ![image](/attachments/a2634cda-a30e-4b5e-bc95-32e925394ae1) - Add optional 0R pads to bias TEC_VSEN instead of using 3V3 power supply ![image](/attachments/e2cfb302-ac7d-4cc4-8aad-6d5c3befa5c1) - Correct the OpAmp Input Polarity for TEC_VSEN - TEC+ should connect to OpAmp IN+ - TEC- should connect to OpAmp IN- ![image](/attachments/76ca26ae-54d6-4d75-b1f7-07ac15a2a7b7) ### BOM Related - Update P/Ns and comments - Place Y169010R0000T9L Precision Power Resistor instead of PDY10R000F and its jumper resistor accordingly - Cannot source PDY10R000F Precision Power Resistor - Place the 5 Pin 2.54mm Pitch MCU Prog Header and assign P/N - Add Screws P/Ns from JLCPCB - Add SMA Jack to SMA Plug Cable - Mount the Jack to front panel and connect it to LD Adapter modulation input - 35V 2u2 PMLCAP is changed to be a 16V version of the same series for lower cost - Footprint on PCB is changed accordingly - 35MU225MC14532 -> 16MU225MB23225 ![image](/attachments/aa09f2f8-39f9-4b2b-a197-4933b7b4828a) ### Front Panel - Complete Front Panel Exploded Assembly and Technical Drawings are drawn in FreeCad are added - Add Output files for production ## Review Major Change: ### Power Related - Add LEDs and TestPoints for all Power Rails - the most important power rails is still accessible even after LD Adapter is installed - Custom Net Clearance Constraints Rules are created for POE_12V and Other Power Nets for safety reason - (Kicad 7 new features) - 1 mm Clearance is maintained ``` (version 1) (rule "PoE PWR Clearance Between GND and PoE AC Input" (constraint clearance (min 1.0mm)) (condition " A.NetClass != B.NetClass && A.NetClass == 'PWR' && B.NetClass == 'POE_PWR' " )) ``` ~~- Replace the input capacitors of LT304x LDOs with C0G/ low ESR Tantalum Capacitor~~ - Use C0G capacitors along the LD Drive Signal Path ![image](/attachments/6330743f-8c77-4126-b204-77063c319af8) - Optimize the number of tantalum capacitors for lower cost - Replace some of the non-critical power stages with Electrolytic capacitor - PoE Output LPF Filter, 12V right after reverse voltage protection stage, 3V3 near Ethernet LNA8742A IC, Digital 12V input ![image](/attachments/ac68ef2a-57ff-4070-b01b-0925b5410c72) ![image](/attachments/ed31a4c4-1755-4b9f-9d3f-68977c266c07) ![image](/attachments/13e7968c-c1ae-4dff-8700-dc9f51373821) ~~Delete redundant tantalum capacitors or Reposition the tantalum capacitors to the LT304x Input for lower microphonics - 9V output tantalum capacitors is replaced by multiple 22u ceramics~~ - Add TAN Caps to all LT304x SET Pin - SET pin connected to the internal Error Amplifier - Using TAN Caps can avoid microphonics noise to be amplified - Datasheet: CSet Max = 22uF - Value is selected with the consideration of physical size constraint and package's ESR ![image](/attachments/e5128619-4929-4d50-a284-b7a73b8b1c0d) - Replace the FB at -6V and +15V LDO input with a Pi LC LPF ![image](/attachments/92a42ec6-fa27-42c2-8b46-fdb15b3a9c93) ### Front Panel and Ports Alignment - Add Front Panel FreeCad Assembly and add the 3D models to the PCB - Extend the board edge so that the ports protrude into the front panel ![image](/attachments/f6809107-b34a-4d52-b931-04a409194df4) - Dashed silkscreen is the Front Panel Edge PCB edge ![image](/attachments/bfb655a3-95fb-4f54-ab5d-b9c4b94b827e) - Add front panel outline for port alignment (in User1 Layer) ![image](/attachments/d16aa5b1-434a-4592-a7cb-ae8ce8b60883) ### Analog Related - Add alternate Footprint LTC6655 Vref IC ![image](/attachments/3d70ef81-8879-4075-8272-0d918b07d79c) ![image](/attachments/612d6cfd-2b92-428d-9749-ccbeef6d7ad7) - Add LPF and Buffer for TEC Driver VREF ![image](/attachments/1f13eef7-468c-46b0-ad35-3d74de471ec7) ### Kirdy LD Adapter - Improve Kirdy LD Adapter 3D Model for checking clearance - Total Vertical Mating Height (from Kirdy PCB Top Layer to the Laser Mount) = 11(Stnadoff) +1.6(LD Adapter Board Thickness + 19(Laser Mount Height) = 31.6mm < 35.3mm(max allowed height) - Add Wurth Elektronik's solder standoffs - Add 2 more mounting holes for Kirdy LD Adapter ![image](/attachments/3400b136-e34c-4200-8a83-8401a66d85c4) ### MCU Extension Headers - Add 12V to the header ![image](/attachments/628ad4ea-4726-4ef4-9cb5-429e4214f7a0) - Add 4 Wurth Elektronik's solder standoffs for the MCU Extension Connectors - Kirdy LD Adapter's SMA Connector should not have clearance issue even if the MCU Extension board is installed. - SMA Cable requires ~3mm being straight before being able to be bent ![image](/attachments/91f5efcb-b258-4cd8-b93b-84bb04c0b22d) ### Others - Add back reference designators on silkscreen for all connectors - USB, SMA, Ethernet, MCU EXT HDR, MCU Programming HDRs, Power Jacks, SWs - Extract and Add some 3D models from Sinara-hw for some footprints ### Major PCB Layout Changes - Routing of Mod_IN Signal is routed closer to the edge - Max Clearance is maintained between digital signal for MCU EXT HDR to reduce cross talk - > 22x trace width of Mod_IN ![image](/attachments/3a393dd7-173d-4c18-8590-237b39f089ea) - Add Via Fencing to Mod_IN Signal ![image](/attachments/844a0f11-0196-4b22-8f65-025a370d5fe3) - 8V LDO circuitry is relocated due to the new mounting hole placement ![image](/attachments/61114434-7480-435c-8d29-b116caf4f12e) - part of then drive stage circuit is repositioned due to the placement of mounting hole - Capacitor placements are improved with the signal path is routed in daisy chain connection topology ![image](/attachments/f476fdad-3ab6-4691-97d7-45c245b825e4) - 4.096 Vref IC for the LD Drive DAC is repositioned to create more distance from MCU signals ![image](/attachments/4aa78186-029f-45f3-b73b-e57d974f296a) - Add at least 1mm clearance between primary and secondary side of PoE ![image](/attachments/aa32e6e4-ffe6-4cc0-9eef-e7a16e1b9129) - Relocate the programming HDRs to a more accessible place ![image](/attachments/12942af3-102e-48e4-aecb-7e5f6a463407) ## General: - Migrate current project from Kicad 6 to Kicad 7 - Components can be marked DNP instead of marking it by setting a DNP value - Correct incorrect MFR_PN and MFR_PN_ALT - See Issue #28 ## Python Scripts to Generate all Production Files ### Usage - For NixOs User, install kicad in nix profile, run the scripts without setting any flags should generate the productions files. - For non-NixOs User, the path to "kicad_netlist_reader.py" scripts and the location of the kicad-builtin 3D models must be specified. - Command to run: `python -m scripts.generate_production_files.py` ## Footprint - Enlarge the courtyard and silkscreen area for PM1202 so that it can be seated flat on the PCB ## Front Panel Design - Port the step file outline and dxf markings to Kicad Project - Marking texts can be modified via Kicad now - Change "fiber" to "laser" - Issue #10 ![image](/attachments/2593325a-c1cc-4275-87c4-47896743c637) - Use a custom font Prison Gothic (Light) Font for all the non-logo text markings - The font is not included in this repo - Font is needed to be installed to the system wide for it to render. - Add a production folder storing the production files ## Schematics: ### Top - Correct Temperature DAC SPI Signals Connections - See Issue #25 for details ![image](/attachments/05515134-0a7a-49d3-a3a6-abd9268a7cd7) - Add Front Panel 3D Model and Kirdy LD Adapter 3D model to the board - Add Mounting Holes for Kirdy LD Adapter - Kirdy LD Adapter has heavy copper thermal mass for laser diode. Extra mounting holes are required to secure the board from coming out. 3D Model Overview: Top: ![image](/attachments/42714904-cee5-4cd3-b838-ee99b845578e) Front Panel View: ![image](/attachments/9e543132-bc3e-46d3-908f-e8878360d805) ### DriveStage - PD TIA and LPF Stage uses TL082Hx - See Issue #19 for details ![image](/attachments/ce5f4eb9-f6a3-401b-9e7a-9de932d9f007) - Add alternate precision power resistor for Drive Stage - MFR_PN: Y169010R0000T9L from Vishay Precision Group ![image](/attachments/f0c92d8a-0730-4b95-bbad-00019754e2a4) - Add a switch to 50Ohm termination to be enabled optionally for modulation signal - TERM_IND connects directly to the STM32 pin - ![image](/attachments/bff8f78e-a111-4a8a-a92a-35ec0acc79bc) ### MCU - Add REF3033 Vref to MCU ADC Vref - To improve the ADC measurement of PD signal through MCU ![image](/attachments/bf8b7edf-0618-479a-ae92-38ee796c5263) - Add 2.54mm pitch redundant programming header - Remove Ethernet PoE Reset as the PoE Power supply circuit is changed - Note: MCU_Rstn Port was passed to reset Ethernet PoE Power ![image](/attachments/1ebc6160-4c55-49e0-9369-0cf64b44e741) ### digital supply - Add soft start to 12V Power Jack ![image](/attachments/2f4a25e0-6e40-4767-adcb-2eb23d54b4d1) - Use a RJ45 PoE Jack without internal rectifier and connect it directly to PM1202 - See Issue #24 ![image](/attachments/14bf46a8-d814-43af-a81f-f82c964e2b88) ![image](/attachments/e9870a7e-89ed-4314-b4be-5e541349f96c) ### thermostat - Add alternate footprint for ADC - AD7172-4BCPZ(QFN32) is added as alternate ADC - Use a separated power filtering network for the alternate ADC ![image](/attachments/af76cff6-9472-4881-b37d-ab7243cee236) - Change AD5680 DAC output range to 0-2V - Follow the output voltage range of Sinara-hw Thermostat v2.2.2 ![image](/attachments/a2634cda-a30e-4b5e-bc95-32e925394ae1) - Fix wrong TEC polarity - See Issue #27 - Fix wrong TEC Driver Current Sense Resistor MFR_PN - See Issue #26 ### Modifications Observed on the Prototype board - Tune the V-I Amplifier Feedback path and LD- Out series RC network ![image](/attachments/c78a0209-a125-4bf9-a32e-402b1ac9ab47) - Change the output 10Ohm power resistor to PDY10R000F ![image](/attachments/507f6dec-86e0-46d4-b2c9-0fc2d8b07b47) - Ethernet Signals are being pulled up now instead of pulling down. ![image](/attachments/7673c6ce-2681-4400-8379-e06db2348790) - Parallel Capacitor at LD DAC Output Resistor - See Issue #22 ![image](/attachments/962941b5-27f6-417b-bd2e-2d87bf66016e) - Modify the freq comp network of Buck converter to improve stability and transient response - See Issue #21 ![image](/attachments/949ac86b-460a-4eb5-97b9-6cd356a83b6e) ### Issues Fixed: Close #10 Close #14 Close #15 Close #24 Close #25 Close #26 Close #27 Close #28
linuswck added 17 commits 2023-10-26 13:32:09 +08:00
linuswck added 12 commits 2023-11-02 15:26:28 +08:00
89dab2b553 sch: Change PoE RJ45 Jack and change PM1202 Symbol
- Use the same PoE RJ45 as sinara-hw thermostat
- Add PM1202 Power input pins (VB+, VB-)
- Remove PoE softstart circuit as PM1202 has inrush current limiting
- Add Pi Filter at the output of PM1202
fcae5b785e sch: Correct SWD Header MF/PN and Update Footprint
- Use Adafuit 4048 Mini SWD Headers
- Silkscreen is modified to indicate orientation of the header
caf69e4a0f symbol: correct RJ45 VC output pin type
- from power input to power output
0c3c8a3fd1 sch: Update power related flags and nets symbols
- Update the symbol from the kicad 7 built-in library
- Remove ERC warnings
2a6ad78f51 pcb: Finish Layout for rev0_3
- Assign MFR_PN for all Components
- schematics changes:
  - drivestage: Add Switch to optionally enable Modulation Signal Termination
  -             Add alternate Precision Power Resistor
  -             Modify the RC network values at TIA LPF Output
  - MCU: Add Redundant 2.54mm pitch Programming Header
  - thermostat: Duplicate the power filter network for alternate Temperature ADC
Owner

Git rebase commits in this PR into a single commit before merging

I don't think this is necessary.

> Git rebase commits in this PR into a single commit before merging I don't think this is necessary.
linuswck added 10 commits 2023-11-10 17:33:46 +08:00
linuswck added 2 commits 2023-11-15 17:15:33 +08:00
de3e034c7a Add Front Panel, Kirdy LD Adapter 3D models
- Update sch, pcb, sym lib, footrprint lib
- Position of Kirdy LD Adapter is relocated so that it is symmetric
41db8612c0 pcb: relocate switches for better accessibility
- modulation depth SW and termination SW are relocated
linuswck force-pushed rev0_3 from c294805dac to 47a30da9b1 2023-11-17 16:00:12 +08:00 Compare
linuswck added 15 commits 2023-11-27 17:41:53 +08:00
20198f5eab drc: Check PWR nets clearance on pri and sec sides
- Pri: PoE PWR nets
- Sec: PWR nets like GND, 3V3 etc
e0989a61f2 Add Front Panel FreeCAD Assembly
- Static Handle
- PCB Brackets
- Kirdy Front Panel Cutout
db54e6cfa8 sch, pcb:Edit PCB shape for connectors to protrude
- Connectors now protrude the front panel
- Align the connectors by the outline generated from 3D Model
- Update the front panel symbol to include the two mounting holes
5f7743698e pcb: Add reference designators for connectors, SWs
- SMA Connector, USB Type C, Power Jack, RJ45
- MCU Programming Headers and Boot 0 Headers
- Termination Resistor SW, Modulation Depth SW
f29c460e72 Add: Footprints and Step Model for Caps
- SMD ELEC: 865080345012
- SMD C0G Ceramic GRMJN65C1H104JE01J
e7a7eee202 sch, pcb: Remove X7R, X5R at input LT304x
- Reduce the number of Tantalum Capacitor Used
- Replace some non critical ones with Electrolytic Caps
f24f037348 sch, pcb: Change kirdy LD adpter connectors
- Add two extra mounting holes for kirdy LD adapter
- Update kirdy LD adapter 3D model
- Update the PCB layout accordingly
linuswck force-pushed rev0_3 from fbe79e7247 to a8ac943190 2023-11-28 11:46:37 +08:00 Compare
Owner

I meant using tantalum caps at the SET pin of LT304x. This is the most sensitive pin.
LT304x has quite good PSRR, but every noise on SET pin is amplified and present at the output.

I meant using tantalum caps at the SET pin of LT304x. This is the most sensitive pin. LT304x has quite good PSRR, but every noise on SET pin is amplified and present at the output.
Author
Member

I meant using tantalum caps at the SET pin of LT304x. This is the most sensitive pin.
LT304x has quite good PSRR, but every noise on SET pin is amplified and present at the output.

Thank you. I get your point now.

> I meant using tantalum caps at the SET pin of LT304x. This is the most sensitive pin. > LT304x has quite good PSRR, but every noise on SET pin is amplified and present at the output. Thank you. I get your point now.
linuswck added 4 commits 2023-11-29 15:07:43 +08:00
74524b70e4 Scripts: Grab correct KICAD7_3DMODEL_DIR now
- Todo: Use default.nix or flake.nix to setup the path
08133e5e95 sch, pcb: Add TAN Caps to all LT304x SET Pin
- Prevent noise due to microphonics to be amplified by internal Amp
- Remove the input TAN Caps as LT304x PSRR is very good
- Replace TAN Caps in the 12V input side to be ELEC Cap
    - Save cost
linuswck added 10 commits 2023-11-30 16:15:58 +08:00
linuswck force-pushed rev0_3 from a3166da3b8 to 901f394ab3 2023-12-13 13:07:34 +08:00 Compare
linuswck added 1 commit 2023-12-13 15:35:55 +08:00
7ac52b7a1b PCB: Correct Y169010R0000T9L Footprint
- Add more space between the pin holes and resistor body
linuswck force-pushed rev0_3 from d00ceee37a to ae7270bae7 2023-12-15 16:58:01 +08:00 Compare
linuswck force-pushed rev0_3 from ae7270bae7 to 6e7143f152 2023-12-15 17:23:56 +08:00 Compare
linuswck changed title from WIP: Kirdy Revision 3 to Kirdy Revision 0_3 2023-12-18 14:32:50 +08:00
linuswck changed title from Kirdy Revision 0_3 to WIP: Kirdy Revision 0_3 2023-12-18 15:53:41 +08:00
linuswck force-pushed rev0_3 from b52d6c7e34 to f3f3e609e5 2023-12-18 16:05:33 +08:00 Compare
linuswck changed title from WIP: Kirdy Revision 0_3 to Kirdy Revision 0_3 2023-12-19 14:27:05 +08:00
linuswck added 1 commit 2023-12-19 17:12:07 +08:00
linuswck force-pushed rev0_3 from 8ec2035c14 to 1a4b4a2484 2023-12-19 17:49:31 +08:00 Compare
sb10q merged commit 1a4b4a2484 into master 2023-12-19 18:30:32 +08:00
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Reference: sinara-hw/kirdy#23
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