Kirdy Revision 0_3 #23

Merged

sb10q merged 1 commits from linuswck/kirdy:rev0_3 into master 2024-08-17 17:37:24 +08:00

Conversation 3 Commits 1 Files Changed 2 +247 -242

linuswck commented 2023-10-26 13:32:08 +08:00

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Progress

• Schematics
• Footprints for new Components used
• PCB Layout(with rev number updated)
• Verify and Fill in the Part Numbers for all components
• Add 3D models to all the headers, switches and physically big components
• Review for Schematics and PCB Layout
• Update the Panel (Issue #10)
  - [ ] Update PDF Schematics
  - [ ] Add scripts to generate production file(Gerber, Drill, Drill Map, Component Placement File, Schematics PDF, Step 3D Model Files)
• Cleanup files and Add screws P/N
• Write flake.nix so that the path is setup there instead of inside the Python Scripts
• Able to generate production files with nix build .
  • BOM, Gerber, Drill, Drill Map, Component Placement File, Schematics PDF, Step 3D Model Files
• PCB is submitted to be fabricated

Related PR: sinara-hw/kirdyAdapter#1
Related New Repo: https://git.m-labs.hk/linuswck/KiCAD_BOM_Generator

Change Log:

Production Related Change:

PCB

• Update the clearance rules and trace width for PCB Manufacturing
  • There is no layout change.
  • min_clearance: 0.088899mm -> 0.09mm
    • Avoid mills to mm conversion error
  • min_copper_edge_clearance: 0.25mm -> 0.3mm
  • min_hole_clearance: 0.199mm -> 0.254mm
  • min_trace_width: 0.08889mm -> 0.09mm

Sch

• A feedback net for TEC DAC is connected to MCU following sinara-hw Thermostat
  
• Add optional 0R pads to bias TEC_VSEN instead of using 3V3 power supply
  
• Correct the OpAmp Input Polarity for TEC_VSEN
  • TEC+ should connect to OpAmp IN+
  • TEC- should connect to OpAmp IN-
    

BOM Related

• Update P/Ns and comments
• Place Y169010R0000T9L Precision Power Resistor instead of PDY10R000F and its jumper resistor accordingly
  • Cannot source PDY10R000F Precision Power Resistor
• Place the 5 Pin 2.54mm Pitch MCU Prog Header and assign P/N
• Add Screws P/Ns from JLCPCB
• Add SMA Jack to SMA Plug Cable
  • Mount the Jack to front panel and connect it to LD Adapter modulation input
• 35V 2u2 PMLCAP is changed to be a 16V version of the same series for lower cost
  • Footprint on PCB is changed accordingly
  • 35MU225MC14532 -> 16MU225MB23225
    

Front Panel

• Complete Front Panel Exploded Assembly and Technical Drawings are drawn in FreeCad are added
• Add Output files for production

Review Major Change:

Power Related

• Add LEDs and TestPoints for all Power Rails
  • the most important power rails is still accessible even after LD Adapter is installed
• Custom Net Clearance Constraints Rules are created for POE_12V and Other Power Nets for safety reason
  • (Kicad 7 new features)
  • 1 mm Clearance is maintained

(version 1)

(rule "PoE PWR Clearance Between GND and PoE AC Input"
	(constraint clearance (min 1.0mm))
	(condition " A.NetClass != B.NetClass && A.NetClass == 'PWR'  && B.NetClass == 'POE_PWR' " ))

- Replace the input capacitors of LT304x LDOs with C0G/ low ESR Tantalum Capacitor

• Use C0G capacitors along the LD Drive Signal Path
  

• Optimize the number of tantalum capacitors for lower cost

  • Replace some of the non-critical power stages with Electrolytic capacitor
    • PoE Output LPF Filter, 12V right after reverse voltage protection stage, 3V3 near Ethernet LNA8742A IC, Digital 12V input
      
      
      

Delete redundant tantalum capacitors or Reposition the tantalum capacitors to the LT304x Input for lower microphonics
- 9V output tantalum capacitors is replaced by multiple 22u ceramics

• Add TAN Caps to all LT304x SET Pin

  • SET pin connected to the internal Error Amplifier
  • Using TAN Caps can avoid microphonics noise to be amplified
  • Datasheet: CSet Max = 22uF
  • Value is selected with the consideration of physical size constraint and package's ESR
    

• Replace the FB at -6V and +15V LDO input with a Pi LC LPF
  

Front Panel and Ports Alignment

• Add Front Panel FreeCad Assembly and add the 3D models to the PCB
  • Extend the board edge so that the ports protrude into the front panel
    
  • Dashed silkscreen is the Front Panel Edge PCB edge
    
• Add front panel outline for port alignment (in User1 Layer)
  

Analog Related

• Add alternate Footprint LTC6655 Vref IC
  
  

• Add LPF and Buffer for TEC Driver VREF
  

Kirdy LD Adapter

• Improve Kirdy LD Adapter 3D Model for checking clearance
  • Total Vertical Mating Height (from Kirdy PCB Top Layer to the Laser Mount) = 11(Stnadoff) +1.6(LD Adapter Board Thickness + 19(Laser Mount Height) = 31.6mm < 35.3mm(max allowed height)
• Add Wurth Elektronik's solder standoffs
• Add 2 more mounting holes for Kirdy LD Adapter
  

MCU Extension Headers

• Add 12V to the header
  
• Add 4 Wurth Elektronik's solder standoffs for the MCU Extension Connectors
• Kirdy LD Adapter's SMA Connector should not have clearance issue even if the MCU Extension board is installed.
  • SMA Cable requires ~3mm being straight before being able to be bent
    

Others

• Add back reference designators on silkscreen for all connectors
  • USB, SMA, Ethernet, MCU EXT HDR, MCU Programming HDRs, Power Jacks, SWs
• Extract and Add some 3D models from Sinara-hw for some footprints

Major PCB Layout Changes

• Routing of Mod_IN Signal is routed closer to the edge

  • Max Clearance is maintained between digital signal for MCU EXT HDR to reduce cross talk

    • 22x trace width of Mod_IN
      

• Add Via Fencing to Mod_IN Signal
  

• 8V LDO circuitry is relocated due to the new mounting hole placement
  

• part of then drive stage circuit is repositioned due to the placement of mounting hole

  • Capacitor placements are improved with the signal path is routed in daisy chain connection topology
    

• 4.096 Vref IC for the LD Drive DAC is repositioned to create more distance from MCU signals
  

• Add at least 1mm clearance between primary and secondary side of PoE
  

• Relocate the programming HDRs to a more accessible place
  

General:

• Migrate current project from Kicad 6 to Kicad 7
  • Components can be marked DNP instead of marking it by setting a DNP value
• Correct incorrect MFR_PN and MFR_PN_ALT
  • See Issue [Rev0_2] Wrong MFR_PN is set (#28)

Python Scripts to Generate all Production Files

Usage

• For NixOs User, install kicad in nix profile, run the scripts without setting any flags should generate the productions files.
• For non-NixOs User, the path to "kicad_netlist_reader.py" scripts and the location of the kicad-builtin 3D models must be specified.
• Command to run: python -m scripts.generate_production_files.py

Footprint

• Enlarge the courtyard and silkscreen area for PM1202 so that it can be seated flat on the PCB

Front Panel Design

• Port the step file outline and dxf markings to Kicad Project

  • Marking texts can be modified via Kicad now

• Change "fiber" to "laser"

  • Issue rename "fiber" on panel (#10)
    

• Use a custom font Prison Gothic (Light) Font for all the non-logo text markings

  • The font is not included in this repo
  • Font is needed to be installed to the system wide for it to render.

• Add a production folder storing the production files

Schematics:

Top

• Correct Temperature DAC SPI Signals Connections
  • See Issue #25 for details
    
• Add Front Panel 3D Model and Kirdy LD Adapter 3D model to the board
• Add Mounting Holes for Kirdy LD Adapter
  • Kirdy LD Adapter has heavy copper thermal mass for laser diode. Extra mounting holes are required to secure the board from coming out.

3D Model Overview:
Top:

Front Panel View:

DriveStage

• PD TIA and LPF Stage uses TL082Hx

  • See Issue #19 for details
    

• Add alternate precision power resistor for Drive Stage

  • MFR_PN: Y169010R0000T9L from Vishay Precision Group
    

• Add a switch to 50Ohm termination to be enabled optionally for modulation signal

  • TERM_IND connects directly to the STM32 pin
  • 

MCU

• Add REF3033 Vref to MCU ADC Vref

  • To improve the ADC measurement of PD signal through MCU
    

• Add 2.54mm pitch redundant programming header

• Remove Ethernet PoE Reset as the PoE Power supply circuit is changed

  • Note: MCU_Rstn Port was passed to reset Ethernet PoE Power
    

digital supply

• Add soft start to 12V Power Jack
  

• Use a RJ45 PoE Jack without internal rectifier and connect it directly to PM1202

  • See Issue [Rev0_2] PoE Power does not work (#24)
    
    

thermostat

• Add alternate footprint for ADC

  • AD7172-4BCPZ(QFN32) is added as alternate ADC
  • Use a separated power filtering network for the alternate ADC
    

• Change AD5680 DAC output range to 0-2V

  • Follow the output voltage range of Sinara-hw Thermostat v2.2.2
    

• Fix wrong TEC polarity

  • See Issue [Rev0_2] Thermostat: TEC Polarity is drawn incorrectly in schematics (#27)

• Fix wrong TEC Driver Current Sense Resistor MFR_PN

  • See Issue [Rev0_2] Thermostat: Wrong MFR_PN for TEC Current Sense Resistor (#26)

Modifications Observed on the Prototype board

• Tune the V-I Amplifier Feedback path and LD- Out series RC network
  

• Change the output 10Ohm power resistor to PDY10R000F
  

• Ethernet Signals are being pulled up now instead of pulling down.
  

• Parallel Capacitor at LD DAC Output Resistor

  • See Issue R8 parallel capacitor (#22)
    

• Modify the freq comp network of Buck converter to improve stability and transient response

  • See Issue [TEST] Power supplies (#21)
    

Issues Fixed:

Close #10
Close #14
Close #15
Close #24
Close #25
Close #26
Close #27
Close #28

# Progress - [x] Schematics - [x] Footprints for new Components used - [x] PCB Layout(with rev number updated) - [x] Verify and Fill in the Part Numbers for all components - [x] Add 3D models to all the headers, switches and physically big components - [x] Review for Schematics and PCB Layout - [x] Update the Panel (Issue #10) ~~- [ ] Update PDF Schematics~~ ~~- [ ] Add scripts to generate production file(Gerber, Drill, Drill Map, Component Placement File, Schematics PDF, Step 3D Model Files)~~ - [x] Cleanup files and Add screws P/N - [x] Write flake.nix so that the path is setup there instead of inside the Python Scripts - [x] Able to generate production files with `nix build .` - BOM, Gerber, Drill, Drill Map, Component Placement File, Schematics PDF, Step 3D Model Files - [ ] PCB is submitted to be fabricated Related PR: https://git.m-labs.hk/sinara-hw/kirdyAdapter/pulls/1 Related New Repo: https://git.m-labs.hk/linuswck/KiCAD_BOM_Generator # Change Log: ## Production Related Change: ### PCB - Update the clearance rules and trace width for PCB Manufacturing - There is no layout change. - min_clearance: 0.088899mm -> 0.09mm - Avoid mills to mm conversion error - min_copper_edge_clearance: 0.25mm -> 0.3mm - min_hole_clearance: 0.199mm -> 0.254mm - min_trace_width: 0.08889mm -> 0.09mm ### Sch - A feedback net for TEC DAC is connected to MCU following sinara-hw Thermostat  - Add optional 0R pads to bias TEC_VSEN instead of using 3V3 power supply  - Correct the OpAmp Input Polarity for TEC_VSEN - TEC+ should connect to OpAmp IN+ - TEC- should connect to OpAmp IN-  ### BOM Related - Update P/Ns and comments - Place Y169010R0000T9L Precision Power Resistor instead of PDY10R000F and its jumper resistor accordingly - Cannot source PDY10R000F Precision Power Resistor - Place the 5 Pin 2.54mm Pitch MCU Prog Header and assign P/N - Add Screws P/Ns from JLCPCB - Add SMA Jack to SMA Plug Cable - Mount the Jack to front panel and connect it to LD Adapter modulation input - 35V 2u2 PMLCAP is changed to be a 16V version of the same series for lower cost - Footprint on PCB is changed accordingly - 35MU225MC14532 -> 16MU225MB23225  ### Front Panel - Complete Front Panel Exploded Assembly and Technical Drawings are drawn in FreeCad are added - Add Output files for production ## Review Major Change: ### Power Related - Add LEDs and TestPoints for all Power Rails - the most important power rails is still accessible even after LD Adapter is installed - Custom Net Clearance Constraints Rules are created for POE_12V and Other Power Nets for safety reason - (Kicad 7 new features) - 1 mm Clearance is maintained ``` (version 1) (rule "PoE PWR Clearance Between GND and PoE AC Input" (constraint clearance (min 1.0mm)) (condition " A.NetClass != B.NetClass && A.NetClass == 'PWR' && B.NetClass == 'POE_PWR' " )) ``` ~~- Replace the input capacitors of LT304x LDOs with C0G/ low ESR Tantalum Capacitor~~ - Use C0G capacitors along the LD Drive Signal Path  - Optimize the number of tantalum capacitors for lower cost - Replace some of the non-critical power stages with Electrolytic capacitor - PoE Output LPF Filter, 12V right after reverse voltage protection stage, 3V3 near Ethernet LNA8742A IC, Digital 12V input    ~~Delete redundant tantalum capacitors or Reposition the tantalum capacitors to the LT304x Input for lower microphonics - 9V output tantalum capacitors is replaced by multiple 22u ceramics~~ - Add TAN Caps to all LT304x SET Pin - SET pin connected to the internal Error Amplifier - Using TAN Caps can avoid microphonics noise to be amplified - Datasheet: CSet Max = 22uF - Value is selected with the consideration of physical size constraint and package's ESR  - Replace the FB at -6V and +15V LDO input with a Pi LC LPF  ### Front Panel and Ports Alignment - Add Front Panel FreeCad Assembly and add the 3D models to the PCB - Extend the board edge so that the ports protrude into the front panel  - Dashed silkscreen is the Front Panel Edge PCB edge  - Add front panel outline for port alignment (in User1 Layer)  ### Analog Related - Add alternate Footprint LTC6655 Vref IC   - Add LPF and Buffer for TEC Driver VREF  ### Kirdy LD Adapter - Improve Kirdy LD Adapter 3D Model for checking clearance - Total Vertical Mating Height (from Kirdy PCB Top Layer to the Laser Mount) = 11(Stnadoff) +1.6(LD Adapter Board Thickness + 19(Laser Mount Height) = 31.6mm < 35.3mm(max allowed height) - Add Wurth Elektronik's solder standoffs - Add 2 more mounting holes for Kirdy LD Adapter  ### MCU Extension Headers - Add 12V to the header  - Add 4 Wurth Elektronik's solder standoffs for the MCU Extension Connectors - Kirdy LD Adapter's SMA Connector should not have clearance issue even if the MCU Extension board is installed. - SMA Cable requires ~3mm being straight before being able to be bent  ### Others - Add back reference designators on silkscreen for all connectors - USB, SMA, Ethernet, MCU EXT HDR, MCU Programming HDRs, Power Jacks, SWs - Extract and Add some 3D models from Sinara-hw for some footprints ### Major PCB Layout Changes - Routing of Mod_IN Signal is routed closer to the edge - Max Clearance is maintained between digital signal for MCU EXT HDR to reduce cross talk - > 22x trace width of Mod_IN  - Add Via Fencing to Mod_IN Signal  - 8V LDO circuitry is relocated due to the new mounting hole placement  - part of then drive stage circuit is repositioned due to the placement of mounting hole - Capacitor placements are improved with the signal path is routed in daisy chain connection topology  - 4.096 Vref IC for the LD Drive DAC is repositioned to create more distance from MCU signals  - Add at least 1mm clearance between primary and secondary side of PoE  - Relocate the programming HDRs to a more accessible place  ## General: - Migrate current project from Kicad 6 to Kicad 7 - Components can be marked DNP instead of marking it by setting a DNP value - Correct incorrect MFR_PN and MFR_PN_ALT - See Issue #28 ## Python Scripts to Generate all Production Files ### Usage - For NixOs User, install kicad in nix profile, run the scripts without setting any flags should generate the productions files. - For non-NixOs User, the path to "kicad_netlist_reader.py" scripts and the location of the kicad-builtin 3D models must be specified. - Command to run: `python -m scripts.generate_production_files.py` ## Footprint - Enlarge the courtyard and silkscreen area for PM1202 so that it can be seated flat on the PCB ## Front Panel Design - Port the step file outline and dxf markings to Kicad Project - Marking texts can be modified via Kicad now - Change "fiber" to "laser" - Issue #10  - Use a custom font Prison Gothic (Light) Font for all the non-logo text markings - The font is not included in this repo - Font is needed to be installed to the system wide for it to render. - Add a production folder storing the production files ## Schematics: ### Top - Correct Temperature DAC SPI Signals Connections - See Issue #25 for details  - Add Front Panel 3D Model and Kirdy LD Adapter 3D model to the board - Add Mounting Holes for Kirdy LD Adapter - Kirdy LD Adapter has heavy copper thermal mass for laser diode. Extra mounting holes are required to secure the board from coming out. 3D Model Overview: Top:  Front Panel View:  ### DriveStage - PD TIA and LPF Stage uses TL082Hx - See Issue #19 for details  - Add alternate precision power resistor for Drive Stage - MFR_PN: Y169010R0000T9L from Vishay Precision Group  - Add a switch to 50Ohm termination to be enabled optionally for modulation signal - TERM_IND connects directly to the STM32 pin -  ### MCU - Add REF3033 Vref to MCU ADC Vref - To improve the ADC measurement of PD signal through MCU  - Add 2.54mm pitch redundant programming header - Remove Ethernet PoE Reset as the PoE Power supply circuit is changed - Note: MCU_Rstn Port was passed to reset Ethernet PoE Power  ### digital supply - Add soft start to 12V Power Jack  - Use a RJ45 PoE Jack without internal rectifier and connect it directly to PM1202 - See Issue #24   ### thermostat - Add alternate footprint for ADC - AD7172-4BCPZ(QFN32) is added as alternate ADC - Use a separated power filtering network for the alternate ADC  - Change AD5680 DAC output range to 0-2V - Follow the output voltage range of Sinara-hw Thermostat v2.2.2  - Fix wrong TEC polarity - See Issue #27 - Fix wrong TEC Driver Current Sense Resistor MFR_PN - See Issue #26 ### Modifications Observed on the Prototype board - Tune the V-I Amplifier Feedback path and LD- Out series RC network  - Change the output 10Ohm power resistor to PDY10R000F  - Ethernet Signals are being pulled up now instead of pulling down.  - Parallel Capacitor at LD DAC Output Resistor - See Issue #22  - Modify the freq comp network of Buck converter to improve stability and transient response - See Issue #21  ### Issues Fixed: Close #10 Close #14 Close #15 Close #24 Close #25 Close #26 Close #27 Close #28

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👍 1

linuswck added 17 commits 2023-10-26 13:32:09 +08:00

Mirgrate to kicad7 fcdabaee9c

sch: R13 Power Resistor change to PDY10R000F 8e5545f9c4

pcb: migrate to kicad 7 5ffc2a1865

sch: Add soft start to 12V PWR Jack input 3ba3ef159e

sch: Fix Issue #15 566bf0317a

sch: Modify dsupply freq_comp network ... 01d0e1d45b

- See Issue #21

sch: Add REF3033 for MCU ADC VREF 893f5220c6

sch: Use TL082 for PD_Mon TIA and LPF Stage 2df59fbce9

sch: LD DAC add parallel Cap to output resistor ... dfeb1ec6a8

- Increase the Mod_In Signal Bandwidth
- See Issue #22

footprint: Correct PM1202 footprint ... e62bf3b8d6

- enlarge courtyard and silkscreen to reflect the clearance requirement so that it can be fully seated onto the PCB

sch: Tune the LD V-I Output Stage Feedback Network ... 1fad3bf64d

- R67 -> 0R
- C175 -> 100pF

sch: Tune LD- Out Series RC Network ... 3a1dce0107

- R98 3R3 -> 10R
- C192 100n PPS -> DNP
- Add C199 2n2 in parallel C192

sch: correct ethernet phy sigs connections to ESD ... f1bda76636

- Pull up eth signals with 100R instead of pull down

sch: Fix Issue #14 f732b9944a

sch: Do not pass MCU RST to ETH ... d2c80458aa

- D3 -> DNP

sch: Support Temp ADC in alternate footprint ... 57e013c9c5

- Issue #12
- Add Alternate AD7172-4BCPZ circuitry, symbol, footprint and 3D model

sch: Set DNP for DNP components 929ff58706

linuswck added 12 commits 2023-11-02 15:26:28 +08:00

sch: Change PoE RJ45 Jack and change PM1202 Symbol ... 89dab2b553

- Use the same PoE RJ45 as sinara-hw thermostat
- Add PM1202 Power input pins (VB+, VB-)
- Remove PoE softstart circuit as PM1202 has inrush current limiting
- Add Pi Filter at the output of PM1202

sch: Correct SWD Header MF/PN and Update Footprint ... fcae5b785e

- Use Adafuit 4048 Mini SWD Headers
- Silkscreen is modified to indicate orientation of the header

sch: Add redundant 2.54mm SWD Header f66625e431

sch: Correct typos in TEC_~{SHDN} ports 86f5addbad

sch: add lpf at TEC_VSEN Buffer Output 395e104575

sch: fix Temperature ADC SPI Connections ... 1f9b4e9900

- Fix Issue #25

symbol: AD7172-4 sets DNC pin to unconnected type b0525c4d74

symbol: correct RJ45 VC output pin type ... caf69e4a0f

- from power input to power output

sch: correct POE_VC* pins name case ... fc02f24131

- PoE_VC* -> POE_VC*

sch: Update power related flags and nets symbols ... 0c3c8a3fd1

- Update the symbol from the kicad 7 built-in library
- Remove ERC warnings

footprint: Add TL082Hx TI SOIC-8 footprint 352f8c075d

pcb: Finish Layout for rev0_3 ... 2a6ad78f51

- Assign MFR_PN for all Components
- schematics changes:
  - drivestage: Add Switch to optionally enable Modulation Signal Termination
  -             Add alternate Precision Power Resistor
  -             Modify the RC network values at TIA LPF Output
  - MCU: Add Redundant 2.54mm pitch Programming Header
  - thermostat: Duplicate the power filter network for alternate Temperature ADC

sb10q commented 2023-11-02 18:38:27 +08:00

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Git rebase commits in this PR into a single commit before merging

I don't think this is necessary.

> Git rebase commits in this PR into a single commit before merging I don't think this is necessary.

linuswck added 10 commits 2023-11-10 17:33:46 +08:00

thermostat: Fix wrong P/N in TEC Current Sense Res ... 7b5df5150f

- Fix Issue #26

sch: Fix incorrect TEC polarity in thermostat ... 7aa84d4d23

- Fix Issue #27

pcb: Fix TEC Polarity Connections to Header ... 13b5f661c5

- Fix Issue #27

pcb: Remove "designed by" silkscreen a30ac45c5f

sch, pcb: exclude MHs and soldering JP from BOM 5ad5914748

scripts: Add scripts to generate production files ... 35da9f8c58

- The following files can be generated from the script.
1. Zipped(Gerber, Drill, Drill Map)
2. Bom,
3. Component Placement
4. Schematics PDF
5. Step Files

sch: Update Title Block Info ... cd679cf0da

- rev0.3 -> rev0_3
- Correct the title of each schematics
- Update the modified time

Remove old production files 7c72afe55f

sch, pcb: Correct MFR/PN and optimize BOM 0b99a8f119

pcb: Add 3D Models 9f3793c8fb

linuswck added 2 commits 2023-11-15 17:15:33 +08:00

Add Front Panel, Kirdy LD Adapter 3D models ... de3e034c7a

- Update sch, pcb, sym lib, footrprint lib
- Position of Kirdy LD Adapter is relocated so that it is symmetric

pcb: relocate switches for better accessibility ... 41db8612c0

- modulation depth SW and termination SW are relocated

linuswck referenced this pull request from sinara-hw/kirdyAdapter 2023-11-17 11:33:41 +08:00

Revise the Kirdy Laser Driver Adapter for Kirdy Rev0_3 #1

linuswck force-pushed rev0_3 from c294805dac to 47a30da9b1 2023-11-17 16:00:12 +08:00 Compare

linuswck added 15 commits 2023-11-27 17:41:53 +08:00

drc: Check PWR nets clearance on pri and sec sides ... 20198f5eab

- Pri: PoE PWR nets
- Sec: PWR nets like GND, 3V3 etc

sch, pcb: Add PWR, POE_PWR netclasses b901f84d0a

3D_Model: Update 204-121ST 13a90dd642

Add Front Panel FreeCAD Assembly ... e0989a61f2

- Static Handle
- PCB Brackets
- Kirdy Front Panel Cutout

sch, pcb:Edit PCB shape for connectors to protrude ... db54e6cfa8

- Connectors now protrude the front panel
- Align the connectors by the outline generated from 3D Model
- Update the front panel symbol to include the two mounting holes

sch, pcb: add 0R for TEC Vref Ouput ... c59eccaa7d

- For debugging if needed

sch, pcb: Add LEDs and TPs to Critical Power Rails 2cbab29c4e

sch, pcb: Add alternate footprint for LTC6655 Vref 24637b4216

sch, pcb: Replace FB of -6V +15V LDO with inductor ... 43903708c3

- Build a Pi LPF on the input side

pcb: Add reference designators for connectors, SWs ... 5f7743698e

- SMA Connector, USB Type C, Power Jack, RJ45
- MCU Programming Headers and Boot 0 Headers
- Termination Resistor SW, Modulation Depth SW

Add: Footprints and Step Model for Caps ... f29c460e72

- SMD ELEC: 865080345012
- SMD C0G Ceramic GRMJN65C1H104JE01J

sch, pcb: Remove X7R, X5R at input LT304x ... e7a7eee202

- Reduce the number of Tantalum Capacitor Used
- Replace some non critical ones with Electrolytic Caps

sch, pcb: Add LPF and Buffer for TEC VREF 95494ee031

sch, pcb: Change kirdy LD adpter connectors ... f24f037348

- Add two extra mounting holes for kirdy LD adapter
- Update kirdy LD adapter 3D model
- Update the PCB layout accordingly

sch, pcb: add tantalum C0G Caps for 8V out LT3045 83506fd3c6

linuswck force-pushed rev0_3 from fbe79e7247 to a8ac943190 2023-11-28 11:46:37 +08:00 Compare

gkasprow commented 2023-11-29 04:42:52 +08:00

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I meant using tantalum caps at the SET pin of LT304x. This is the most sensitive pin.
LT304x has quite good PSRR, but every noise on SET pin is amplified and present at the output.

I meant using tantalum caps at the SET pin of LT304x. This is the most sensitive pin. LT304x has quite good PSRR, but every noise on SET pin is amplified and present at the output.

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linuswck commented 2023-11-29 10:55:28 +08:00

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I meant using tantalum caps at the SET pin of LT304x. This is the most sensitive pin.
LT304x has quite good PSRR, but every noise on SET pin is amplified and present at the output.

Thank you. I get your point now.

> I meant using tantalum caps at the SET pin of LT304x. This is the most sensitive pin. > LT304x has quite good PSRR, but every noise on SET pin is amplified and present at the output. Thank you. I get your point now.

linuswck added 4 commits 2023-11-29 15:07:43 +08:00

sch: Add Mounting Screw Symbol and MFR/PN f558f62313

Reassign Reference Designators for all Symbols 13720b3ccc

Scripts: Grab correct KICAD7_3DMODEL_DIR now ... 74524b70e4

- Todo: Use default.nix or flake.nix to setup the path

sch, pcb: Add TAN Caps to all LT304x SET Pin ... 08133e5e95

- Prevent noise due to microphonics to be amplified by internal Amp
- Remove the input TAN Caps as LT304x PSRR is very good
- Replace TAN Caps in the 12V input side to be ELEC Cap
    - Save cost

linuswck added 10 commits 2023-11-30 16:15:58 +08:00

Add Front Panel MFR_PN 76480a3679

Add Manufacturer into PM1202's Value & Comment c053eca22a

sch: Add install Instructions for Power Resistor 66b6cd28d5

pcb: Relocate programming hdrs to an accessible place ... 401802709e

- Even after the MCU EXT mezzanine is installed

pcb: Add GND and via fencing for Mod_IN signal 007ba75003

sch: Correct Front Panel Kit MRF/PN & Value typo 56ef8302a7

pcb: relocate programming hdrs ... cc64790270

- prev locations block Internal SMA cable

Front Panel: Relocate markings to diff layers ... 83bd5e9a03

- Move the markings to different layers for generating prod docs
- Add comments in the drawings pdf

sch: Not to include TPs in BOM. Add prod comments ... 8b3d5d8e44

- LTC6655 Vref adds production comments

pcb: Update PN and properties of symbols 3b7fbdb2be

linuswck force-pushed rev0_3 from a3166da3b8 to 901f394ab3 2023-12-13 13:07:34 +08:00 Compare

linuswck added 1 commit 2023-12-13 15:35:55 +08:00

PCB: Correct Y169010R0000T9L Footprint ... 7ac52b7a1b

- Add more space between the pin holes and resistor body

linuswck force-pushed rev0_3 from d00ceee37a to ae7270bae7 2023-12-15 16:58:01 +08:00 Compare

linuswck force-pushed rev0_3 from ae7270bae7 to 6e7143f152 2023-12-15 17:23:56 +08:00 Compare

linuswck changed title from WIP: Kirdy Revision 3 to Kirdy Revision 0_3 2023-12-18 14:32:50 +08:00

linuswck changed title from Kirdy Revision 0_3 to WIP: Kirdy Revision 0_3 2023-12-18 15:53:41 +08:00

linuswck force-pushed rev0_3 from b52d6c7e34 to f3f3e609e5 2023-12-18 16:05:33 +08:00 Compare

linuswck changed title from WIP: Kirdy Revision 0_3 to Kirdy Revision 0_3 2023-12-19 14:27:05 +08:00

linuswck added 1 commit 2023-12-19 17:12:07 +08:00

sch, pcb: Add 0R to use TEC_VREF to bias TEC_VSEN ... f847cfadb4

- Optional

linuswck force-pushed rev0_3 from 8ec2035c14 to 1a4b4a2484 2023-12-19 17:49:31 +08:00 Compare

sb10q merged commit 1a4b4a2484 into master 2023-12-19 18:30:32 +08:00

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Reference: sinara-hw/kirdy#23

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