L8 may cause damage to Q9 when one switches off. Add a capacitor or TVS before inductor
why do you use R107...R110? They damp the Ethernet signal, moreover they cause DC current flowing through Ethernet transformer and may saturate it.
the MAX5719 has 5V CMOS logic levels. H state is >3.5V. The STM supplied from 3.3V is unable to drive it correctly. It probably works, but with temperature changes or process variation it may cause issues
I recommend a buffer/translator anyway to damp the digital noise from CPU that couples with DAC analog circuit.
U3, U4 are supplied from charge pump which has 100mA current capability. However they need to output several mAs of current. I'd increase R7 and R8 to make sure they won't overload the supply
I'd add more sophisticated LD_SHORT driving circuit to make sure somebody won't enable relay by chance during i.e. CPU debugging. Some flip flop or so.
Is LM358 precision enough for photodiode feedback? You use much better opamps in the circuit already.
general rule - when connecting component pads make sure that both have thermal relief or not. When one pad has solid copper and other pad has the traces, it may cause tombstone effect during assembly.
Example: C191 and many caps
avoid via-in-pad. It will suck the tin and cause poor contact. Example C191 and many caps. It works when you order capped vias but it is an additional process which is usually not for free. A lot of vias in pad also cause tombstone effect due to different thermal capacitance
AD7172 is very close to the power converter. Too close. Add they share the same ground plane. I recommend making a cutout in all copper planes in such way that driver return current doesn't flow under the ADC
There is a lot of space at the PCB "bottom-right" side
TPS54620 layout is far from optimal. The switching current loop are is unnecesairly big causing the noise in the GND plane and excessive EMI. Follow the datasheet guideline.
- [ ] L8 may cause damage to Q9 when one switches off. Add a capacitor or TVS before inductor
- [ ] why do you use R107...R110? They damp the Ethernet signal, moreover they cause DC current flowing through Ethernet transformer and may saturate it.
- [ ] the MAX5719 has 5V CMOS logic levels. H state is >3.5V. The STM supplied from 3.3V is unable to drive it correctly. It probably works, but with temperature changes or process variation it may cause issues
- [ ] I recommend a buffer/translator anyway to damp the digital noise from CPU that couples with DAC analog circuit.
- [ ] U3, U4 are supplied from charge pump which has 100mA current capability. However they need to output several mAs of current. I'd increase R7 and R8 to make sure they won't overload the supply
- [ ] I'd add more sophisticated LD_SHORT driving circuit to make sure somebody won't enable relay by chance during i.e. CPU debugging. Some flip flop or so.
- [ ] Is LM358 precision enough for photodiode feedback? You use much better opamps in the circuit already.
- [ ] AD5680 is NRND. At least Mouser claims so [https://eu.mouser.com/ProductDetail/Analog-Devices/AD5680?qs=5aG0NVq1C4zd9fc7y9CwwQ%3D%3D](https://)
- [ ] why revision ID is set to 1111 ?
- [ ] I'd add an LC filter at the U20 supply
PCB
- [ ] general rule - when connecting component pads make sure that both have thermal relief or not. When one pad has solid copper and other pad has the traces, it may cause tombstone effect during assembly.
Example: C191 and many caps
- [ ] avoid via-in-pad. It will suck the tin and cause poor contact. Example C191 and many caps. It works when you order capped vias but it is an additional process which is usually not for free. A lot of vias in pad also cause tombstone effect due to different thermal capacitance
- [ ] AD7172 is very close to the power converter. Too close. Add they share the same ground plane. I recommend making a cutout in all copper planes in such way that driver return current doesn't flow under the ADC
There is a lot of space at the PCB "bottom-right" side
- [ ] TPS54620 layout is far from optimal. The switching current loop are is unnecesairly big causing the noise in the GND plane and excessive EMI. Follow the datasheet guideline.
Thanks for the detailed review and comments, much appreciated.
I'd add more sophisticated LD_SHORT driving circuit to make sure somebody won't enable relay by chance during i.e. CPU debugging. Some flip flop or so.
There are many different ways to break the diode during debugging, just don't connect an expensive one while debugging :)
Is LM358 precision enough for photodiode feedback? You use much better opamps in the circuit already.
Correct me if I'm wrong - but this is a diagnostics photodiode which only gives a rough indication of the laser power and I believe a precision measurement is not necessary there.
Thanks for the detailed review and comments, much appreciated.
> I'd add more sophisticated LD_SHORT driving circuit to make sure somebody won't enable relay by chance during i.e. CPU debugging. Some flip flop or so.
There are many different ways to break the diode during debugging, just don't connect an expensive one while debugging :)
> Is LM358 precision enough for photodiode feedback? You use much better opamps in the circuit already.
Correct me if I'm wrong - but this is a diagnostics photodiode which only gives a rough indication of the laser power and I believe a precision measurement is not necessary there.
match the DC jack, USB and Ethernet connectors fronts with panel.
I'd recommend using THT version of laser module connectors - the SMT may fall off
I'd recommend adding fixing holes to the laser module
R105 and R106 may collide with panel assembly
aestethics
mark dip-switch functions on silkscreen
safety
the PoE converter primary side clearance to GND plane is far too low. It should be min 0.5mm or higher. The same applies to 4.7nF capacitor to GND via clearance and NET(R57-pad2) net clearance.
mechanics
- [ ] match the DC jack, USB and Ethernet connectors fronts with panel.
- [ ] I'd recommend using THT version of laser module connectors - the SMT may fall off
- [ ] I'd recommend adding fixing holes to the laser module
- [ ] R105 and R106 may collide with panel assembly
aestethics
- [ ] mark dip-switch functions on silkscreen
safety
- [ ] the PoE converter primary side clearance to GND plane is far too low. It should be min 0.5mm or higher. The same applies to 4.7nF capacitor to GND via clearance and NET(R57-pad2) net clearance.
Thanks for the detailed review and comments, much appreciated.
I'd add more sophisticated LD_SHORT driving circuit to make sure somebody won't enable relay by chance during i.e. CPU debugging. Some flip flop or so.
There are many different ways to break the diode during debugging, just don't connect an expensive one while debugging :)
Sure, we got such requirement from laser module experts when designing ultra-low noise laser driver for ai-artiq project. Single D-flip flop does the job.
Is LM358 precision enough for photodiode feedback? You use much better opamps in the circuit already.
Correct me if I'm wrong - but this is a diagnostics photodiode which only gives a rough indication of the laser power and I believe a precision measurement is not necessary there.
Just asking what's the requirement. For monitoring it's fine. For stabilisation it may be not sufficient.
Thanks for the detailed review and comments, much appreciated.
I'd add more sophisticated LD_SHORT driving circuit to make sure somebody won't enable relay by chance during i.e. CPU debugging. Some flip flop or so.
There are many different ways to break the diode during debugging, just don't connect an expensive one while debugging :)
Sure, we got such requirement from laser module experts when designing ultra-low noise laser driver for ai-artiq project. Single D-flip flop does the job.
Is LM358 precision enough for photodiode feedback? You use much better opamps in the circuit already.
Correct me if I'm wrong - but this is a diagnostics photodiode which only gives a rough indication of the laser power and I believe a precision measurement is not necessary there.
Just asking what's the requirement. For monitoring it's fine. For stabilisation it may be not sufficient.
L8 may cause damage to Q9 when one switches off. Add a capacitor or TVS before inductor
Noted.
why do you use R107...R110? They damp the Ethernet signal, moreover they cause DC current flowing through Ethernet transformer and may saturate it.
This is a schematic error, the resistors are supposed to be around 50 ohms and pull up to AVDDT_PHY and not pull down to ground, same as thermostat.
the MAX5719 has 5V CMOS logic levels. H state is >3.5V. The STM supplied from 3.3V is unable to drive it correctly. It probably works, but with temperature changes or process variation it may cause issues.
Good catch, indeed the DAC was working fine in V1 testing, so the issue escaped my attention.
I recommend a buffer/translator anyway to damp the digital noise from CPU that couples with DAC analog circuit.
Noted.
U3, U4 are supplied from charge pump which has 100mA current capability. However they need to output several mAs of current. I'd increase R7 and R8 to make sure they won't overload the supply
R7 and R8 is chosen to minimise noise. I've ran calculations and tested the V1 board, there's no indication of the charge pump being overloaded.
I'd add more sophisticated LD_SHORT driving circuit to make sure somebody won't enable relay by chance during i.e. CPU debugging. Some flip flop or so.
Reasonable point, will see if there's a more reliable and robust way of controlling the relay, without introducing more issues.
Is LM358 precision enough for photodiode feedback? You use much better opamps in the circuit already.
@sb10q 's idea, precision is not required. Also the LM358 is quite low power so it won't increase the -6v consumption much.
AD5680 is NRD
Yes, but one of the design goals was to reuse the thermostat ADC (also hard to source) and DAC to minimise software development effort.
why revision ID is set to 1111
Should have been marked, but the resistors will be selectively populated.
I'd add an LC filter at the U20 supply
Fair point.
general rule - when connecting component pads make sure that both have thermal relief or not. When one pad has solid copper and other pad has the traces, it may cause tombstone effect during assembly.
Example: C191 and many caps
I am aware of the issue, but kicad does not make it easy or possible to have different thermal relief settings for different type of pads, especially within the same polygon. So pads that require low impedance or high current connections must share the same relief settings as small parts.
To make things easier and consistent I just decided to keep all as solid connections. It is not ideal for sure and I'll see if there's something I can do in that regard.
avoid via-in-pad. It will suck the tin and cause poor contact. Example C191 and many caps. It works when you order capped vias but it is an additional process which is usually not for free. A lot of vias in pad also cause tombstone effect due to different thermal capacitance
I had this in mind, but in my experience vias with 0.2mm drills and masked bottom side does not introduce issues with solder wicking into holes much.
I also only used via in pad for large pads where more solder paste will be applied.
AD7172 is very close to the power converter. Too close. Add they share the same ground plane. I recommend making a cutout in all copper planes in such way that driver return current doesn't flow under the ADC
There is a lot of space at the PCB "bottom-right" side
Noted. I don't like cutting planes, especially ground planes, as it is easy to create EMI issues if not done correctly. Perhaps I'll look into moving the ADC physically further away from the TEC chip.
TPS54620 layout is far from optimal. The switching current loop are is unnecesairly big causing the noise in the GND plane and excessive EMI. Follow the datasheet guideline.
Noted. The most problematic loop in a buck regulator is the input loop, and the capacitors are placed very close to the input pins. However the return path for the capacitor to ground is indeed not optimal. A top layer ground pour should improve things. Otherwise I don't think the layout is too problematic.
Thank you very much for the valuable feedback.
> L8 may cause damage to Q9 when one switches off. Add a capacitor or TVS before inductor
Noted.
> why do you use R107...R110? They damp the Ethernet signal, moreover they cause DC current flowing through Ethernet transformer and may saturate it.
This is a schematic error, the resistors are supposed to be around 50 ohms and pull up to AVDDT_PHY and not pull down to ground, same as thermostat.
> the MAX5719 has 5V CMOS logic levels. H state is >3.5V. The STM supplied from 3.3V is unable to drive it correctly. It probably works, but with temperature changes or process variation it may cause issues.
Good catch, indeed the DAC was working fine in V1 testing, so the issue escaped my attention.
> I recommend a buffer/translator anyway to damp the digital noise from CPU that couples with DAC analog circuit.
Noted.
> U3, U4 are supplied from charge pump which has 100mA current capability. However they need to output several mAs of current. I'd increase R7 and R8 to make sure they won't overload the supply
R7 and R8 is chosen to minimise noise. I've ran calculations and tested the V1 board, there's no indication of the charge pump being overloaded.
> I'd add more sophisticated LD_SHORT driving circuit to make sure somebody won't enable relay by chance during i.e. CPU debugging. Some flip flop or so.
Reasonable point, will see if there's a more reliable and robust way of controlling the relay, without introducing more issues.
> Is LM358 precision enough for photodiode feedback? You use much better opamps in the circuit already.
@sb10q 's idea, precision is not required. Also the LM358 is quite low power so it won't increase the -6v consumption much.
> AD5680 is NRD
Yes, but one of the design goals was to reuse the thermostat ADC (also hard to source) and DAC to minimise software development effort.
> why revision ID is set to 1111
Should have been marked, but the resistors will be selectively populated.
> I'd add an LC filter at the U20 supply
Fair point.
> general rule - when connecting component pads make sure that both have thermal relief or not. When one pad has solid copper and other pad has the traces, it may cause tombstone effect during assembly.
Example: C191 and many caps
I am aware of the issue, but kicad does not make it easy or possible to have different thermal relief settings for different type of pads, especially within the same polygon. So pads that require low impedance or high current connections must share the same relief settings as small parts.
To make things easier and consistent I just decided to keep all as solid connections. It is not ideal for sure and I'll see if there's something I can do in that regard.
> avoid via-in-pad. It will suck the tin and cause poor contact. Example C191 and many caps. It works when you order capped vias but it is an additional process which is usually not for free. A lot of vias in pad also cause tombstone effect due to different thermal capacitance
I had this in mind, but in my experience vias with 0.2mm drills and masked bottom side does not introduce issues with solder wicking into holes much.
https://assets.cree-led.com/a/da/x/XLamp-PCB-Thermal.pdf
In page 6, Cree also suggest the same.
I also only used via in pad for large pads where more solder paste will be applied.
> AD7172 is very close to the power converter. Too close. Add they share the same ground plane. I recommend making a cutout in all copper planes in such way that driver return current doesn't flow under the ADC
There is a lot of space at the PCB "bottom-right" side
Noted. I don't like cutting planes, especially ground planes, as it is easy to create EMI issues if not done correctly. Perhaps I'll look into moving the ADC physically further away from the TEC chip.
> TPS54620 layout is far from optimal. The switching current loop are is unnecesairly big causing the noise in the GND plane and excessive EMI. Follow the datasheet guideline.
Noted. The most problematic loop in a buck regulator is the input loop, and the capacitors are placed very close to the input pins. However the return path for the capacitor to ground is indeed not optimal. A top layer ground pour should improve things. Otherwise I don't think the layout is too problematic.
Just asking what's the requirement. For monitoring it's fine. For stabilisation it may be not sufficient.
This reminds me there are some telecom butterfly modules with integrated Fabry-Perot interferometers for wavelength stabilization - but I don't have experience with them. There would be two of them though, in addition to the power monitor PD. Might be niche enough that the corresponding circuitry could go on the laser adapter board.
> Just asking what's the requirement. For monitoring it's fine. For stabilisation it may be not sufficient.
This reminds me there are some telecom butterfly modules with integrated Fabry-Perot interferometers for wavelength stabilization - but I don't have experience with them. There would be two of them though, in addition to the power monitor PD. Might be niche enough that the corresponding circuitry could go on the laser adapter board.
U3, U4 are supplied from charge pump which has 100mA current capability. However they need to output several mAs of current. I'd increase R7 and R8 to make sure they won't overload the supply
R7 and R8 is chosen to minimise noise. I've ran calculations and tested the V1 board, there's no indication of the charge pump being overloaded.
did you check it with both opamps having min/max outputs?
TPS54620 layout is far from optimal. The switching current loop are is unnecesairly big causing the noise in the GND plane and excessive EMI. Follow the datasheet guideline.
Noted. The most problematic loop in a buck regulator is the input loop, and the capacitors are placed very close to the input pins. However the return path for the capacitor to ground is indeed not optimal. A top layer ground pour should improve things. Otherwise I don't think the layout is too problematic.
avoid via-in-pad. It will suck the tin and cause poor contact. Example C191 and many caps. It works when you order capped vias but it is an additional process which is usually not for free. A lot of vias in pad also cause tombstone effect due to different thermal capacitance
I had this in mind, but in my experience vias with 0.2mm drills and masked bottom side does not introduce issues with solder wicking into holes much.
you can apply some solid copper and distribute the vias around pads.
I am aware of the issue, but kicad does not make it easy or possible to have different thermal relief settings for different type of pads, especially within the same polygon. So pads that require low impedance or high current connections must share the same relief settings as small parts.
are you sure? There is an option in every polygon properties. You can make all thermal relief by default and only ones requiring low thermal resistance solid. Anyway, the measurable difference occurs in GHz frequency area. In our case it doesn't matter. Impedance of 0.5mm wide, 0.25mm long trace is neglidgible. If you have 4 of them it's even lower.
U3, U4 are supplied from charge pump which has 100mA current capability. However they need to output several mAs of current. I'd increase R7 and R8 to make sure they won't overload the supply
R7 and R8 is chosen to minimise noise. I've ran calculations and tested the V1 board, there's no indication of the charge pump being overloaded.
did you check it with both opamps having min/max outputs?
TPS54620 layout is far from optimal. The switching current loop are is unnecesairly big causing the noise in the GND plane and excessive EMI. Follow the datasheet guideline.
Noted. The most problematic loop in a buck regulator is the input loop, and the capacitors are placed very close to the input pins. However the return path for the capacitor to ground is indeed not optimal. A top layer ground pour should improve things. Otherwise I don't think the layout is too problematic.
It's not about capacitors being close to the input pins but the loop area
here is a paper that explains what I mean
https://www.analog.com/cn/analog-dialogue/articles/reducing-ground-bounce-in-dc-to-dc-converters.html
avoid via-in-pad. It will suck the tin and cause poor contact. Example C191 and many caps. It works when you order capped vias but it is an additional process which is usually not for free. A lot of vias in pad also cause tombstone effect due to different thermal capacitance
I had this in mind, but in my experience vias with 0.2mm drills and masked bottom side does not introduce issues with solder wicking into holes much.
you can apply some solid copper and distribute the vias around pads.
I am aware of the issue, but kicad does not make it easy or possible to have different thermal relief settings for different type of pads, especially within the same polygon. So pads that require low impedance or high current connections must share the same relief settings as small parts.
are you sure? There is an option in every polygon properties. You can make all thermal relief by default and only ones requiring low thermal resistance solid. Anyway, the measurable difference occurs in GHz frequency area. In our case it doesn't matter. Impedance of 0.5mm wide, 0.25mm long trace is neglidgible. If you have 4 of them it's even lower.
Just asking what's the requirement. For monitoring it's fine. For stabilisation it may be not sufficient.
This reminds me there are some telecom butterfly modules with integrated Fabry-Perot interferometers for wavelength stabilization - but I don't have experience with them. There would be two of them though, in addition to the power monitor PD. Might be niche enough that the corresponding circuitry could go on the laser adapter board.
Maybe add I2C/spi lines to the laser header to support them?
Just asking what's the requirement. For monitoring it's fine. For stabilisation it may be not sufficient.
This reminds me there are some telecom butterfly modules with integrated Fabry-Perot interferometers for wavelength stabilization - but I don't have experience with them. There would be two of them though, in addition to the power monitor PD. Might be niche enough that the corresponding circuitry could go on the laser adapter board.
Maybe add I2C/spi lines to the laser header to support them?
AD5680 is NRD
Yes, but one of the design goals was to reuse the thermostat ADC (also hard to source) and DAC to minimise software development effort.
One can use DAC in different package like AD5680BRJZ-1500RL7
AD5680 is NRD
Yes, but one of the design goals was to reuse the thermostat ADC (also hard to source) and DAC to minimise software development effort.
One can use DAC in different package like AD5680BRJZ-1500RL7
Interesting read. I still need some convincing and perhaps some simulations and testing to be fully on board with the idea of cutting ground planes to shape return current to reduce ground bounce. Anyways I'll reconsider the layout of the buck converter.
you can apply some solid copper and distribute the vias around pads.
For most of the via under pads situations yes, but for the thermal vias under power hungry chips I think it is still better to have via under thermal pad.
are you sure? There is an option in every polygon properties. You can make all thermal relief by default and only ones requiring low thermal resistance solid. Anyway, the measurable difference occurs in GHz frequency area. In our case it doesn't matter. Impedance of 0.5mm wide, 0.25mm long trace is neglidgible. If you have 4 of them it's even lower.
Noted, thanks.
> did you check it with both opamps having min/max outputs?
Will double check.
> It's not about capacitors being close to the input pins but the loop area
here is a paper that explains what I mean
https://www.analog.com/cn/analog-dialogue/articles/reducing-ground-bounce-in-dc-to-dc-converters.html
Interesting read. I still need some convincing and perhaps some simulations and testing to be fully on board with the idea of cutting ground planes to shape return current to reduce ground bounce. Anyways I'll reconsider the layout of the buck converter.
I was thinking more about EMI rather than ground bounce when I mentioned input capacitor placement, which is also important according to this https://www.richtek.com/Design%20Support/Technical%20Document/AN045
> you can apply some solid copper and distribute the vias around pads.
For most of the via under pads situations yes, but for the thermal vias under power hungry chips I think it is still better to have via under thermal pad.
> are you sure? There is an option in every polygon properties. You can make all thermal relief by default and only ones requiring low thermal resistance solid. Anyway, the measurable difference occurs in GHz frequency area. In our case it doesn't matter. Impedance of 0.5mm wide, 0.25mm long trace is neglidgible. If you have 4 of them it's even lower.
Noted, thanks.
AD5680 is NRD
Yes, but one of the design goals was to reuse the thermostat ADC (also hard to source) and DAC to minimise software development effort.
One can use DAC in different package like AD5680BRJZ-1500RL7
This is what we sourced to populate the V1 board.
>
>
> AD5680 is NRD
>
> Yes, but one of the design goals was to reuse the thermostat ADC (also hard to source) and DAC to minimise software development effort.
>
> One can use DAC in different package like AD5680BRJZ-1500RL7
This is what we sourced to populate the V1 board.
For most of the via under pads situations yes, but for the thermal vias under power hungry chips I think it is still better to have via under thermal pad.
Yes, you also need the vias to suck the tin otherwise the chip will float :)
Make sure you open the vias on the other side of the PCB to not make "acid pockets" which will shorten the PCB lifetime.
Either vias are masked on both sides or opened on both side.
For most of the via under pads situations yes, but for the thermal vias under power hungry chips I think it is still better to have via under thermal pad.
Yes, you also need the vias to suck the tin otherwise the chip will float :)
Make sure you open the vias on the other side of the PCB to not make "acid pockets" which will shorten the PCB lifetime.
Either vias are masked on both sides or opened on both side.
PCB
Example: C191 and many caps
There is a lot of space at the PCB "bottom-right" side
Thanks for the detailed review and comments, much appreciated.
There are many different ways to break the diode during debugging, just don't connect an expensive one while debugging :)
Correct me if I'm wrong - but this is a diagnostics photodiode which only gives a rough indication of the laser power and I believe a precision measurement is not necessary there.
mechanics
aestethics
safety
Sure, we got such requirement from laser module experts when designing ultra-low noise laser driver for ai-artiq project. Single D-flip flop does the job.
Just asking what's the requirement. For monitoring it's fine. For stabilisation it may be not sufficient.
Thank you very much for the valuable feedback.
Noted.
This is a schematic error, the resistors are supposed to be around 50 ohms and pull up to AVDDT_PHY and not pull down to ground, same as thermostat.
Good catch, indeed the DAC was working fine in V1 testing, so the issue escaped my attention.
Noted.
R7 and R8 is chosen to minimise noise. I've ran calculations and tested the V1 board, there's no indication of the charge pump being overloaded.
Reasonable point, will see if there's a more reliable and robust way of controlling the relay, without introducing more issues.
@sb10q 's idea, precision is not required. Also the LM358 is quite low power so it won't increase the -6v consumption much.
Yes, but one of the design goals was to reuse the thermostat ADC (also hard to source) and DAC to minimise software development effort.
Should have been marked, but the resistors will be selectively populated.
Fair point.
I am aware of the issue, but kicad does not make it easy or possible to have different thermal relief settings for different type of pads, especially within the same polygon. So pads that require low impedance or high current connections must share the same relief settings as small parts.
To make things easier and consistent I just decided to keep all as solid connections. It is not ideal for sure and I'll see if there's something I can do in that regard.
I had this in mind, but in my experience vias with 0.2mm drills and masked bottom side does not introduce issues with solder wicking into holes much.
https://assets.cree-led.com/a/da/x/XLamp-PCB-Thermal.pdf
In page 6, Cree also suggest the same.
I also only used via in pad for large pads where more solder paste will be applied.
Noted. I don't like cutting planes, especially ground planes, as it is easy to create EMI issues if not done correctly. Perhaps I'll look into moving the ADC physically further away from the TEC chip.
Noted. The most problematic loop in a buck regulator is the input loop, and the capacitors are placed very close to the input pins. However the return path for the capacitor to ground is indeed not optimal. A top layer ground pour should improve things. Otherwise I don't think the layout is too problematic.
This reminds me there are some telecom butterfly modules with integrated Fabry-Perot interferometers for wavelength stabilization - but I don't have experience with them. There would be two of them though, in addition to the power monitor PD. Might be niche enough that the corresponding circuitry could go on the laser adapter board.
did you check it with both opamps having min/max outputs?
It's not about capacitors being close to the input pins but the loop area
here is a paper that explains what I mean
https://www.analog.com/cn/analog-dialogue/articles/reducing-ground-bounce-in-dc-to-dc-converters.html
you can apply some solid copper and distribute the vias around pads.
are you sure? There is an option in every polygon properties. You can make all thermal relief by default and only ones requiring low thermal resistance solid. Anyway, the measurable difference occurs in GHz frequency area. In our case it doesn't matter. Impedance of 0.5mm wide, 0.25mm long trace is neglidgible. If you have 4 of them it's even lower.
Maybe add I2C/spi lines to the laser header to support them?
One can use DAC in different package like AD5680BRJZ-1500RL7
Will double check.
Interesting read. I still need some convincing and perhaps some simulations and testing to be fully on board with the idea of cutting ground planes to shape return current to reduce ground bounce. Anyways I'll reconsider the layout of the buck converter.
I was thinking more about EMI rather than ground bounce when I mentioned input capacitor placement, which is also important according to this https://www.richtek.com/Design%20Support/Technical%20Document/AN045
For most of the via under pads situations yes, but for the thermal vias under power hungry chips I think it is still better to have via under thermal pad.
Noted, thanks.
This is what we sourced to populate the V1 board.
Yes, you also need the vias to suck the tin otherwise the chip will float :)
Make sure you open the vias on the other side of the PCB to not make "acid pockets" which will shorten the PCB lifetime.
Either vias are masked on both sides or opened on both side.