sch/pcb review #13
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PCB
Example: C191 and many caps
There is a lot of space at the PCB "bottom-right" side
Thanks for the detailed review and comments, much appreciated.
There are many different ways to break the diode during debugging, just don't connect an expensive one while debugging :)
Correct me if I'm wrong - but this is a diagnostics photodiode which only gives a rough indication of the laser power and I believe a precision measurement is not necessary there.
mechanics
aestethics
safety
Sure, we got such requirement from laser module experts when designing ultra-low noise laser driver for ai-artiq project. Single D-flip flop does the job.
Just asking what's the requirement. For monitoring it's fine. For stabilisation it may be not sufficient.
Thank you very much for the valuable feedback.
Noted.
This is a schematic error, the resistors are supposed to be around 50 ohms and pull up to AVDDT_PHY and not pull down to ground, same as thermostat.
Good catch, indeed the DAC was working fine in V1 testing, so the issue escaped my attention.
Noted.
R7 and R8 is chosen to minimise noise. I've ran calculations and tested the V1 board, there's no indication of the charge pump being overloaded.
Reasonable point, will see if there's a more reliable and robust way of controlling the relay, without introducing more issues.
@sb10q 's idea, precision is not required. Also the LM358 is quite low power so it won't increase the -6v consumption much.
Yes, but one of the design goals was to reuse the thermostat ADC (also hard to source) and DAC to minimise software development effort.
Should have been marked, but the resistors will be selectively populated.
Fair point.
I am aware of the issue, but kicad does not make it easy or possible to have different thermal relief settings for different type of pads, especially within the same polygon. So pads that require low impedance or high current connections must share the same relief settings as small parts.
To make things easier and consistent I just decided to keep all as solid connections. It is not ideal for sure and I'll see if there's something I can do in that regard.
I had this in mind, but in my experience vias with 0.2mm drills and masked bottom side does not introduce issues with solder wicking into holes much.
https://assets.cree-led.com/a/da/x/XLamp-PCB-Thermal.pdf
In page 6, Cree also suggest the same.
I also only used via in pad for large pads where more solder paste will be applied.
Noted. I don't like cutting planes, especially ground planes, as it is easy to create EMI issues if not done correctly. Perhaps I'll look into moving the ADC physically further away from the TEC chip.
Noted. The most problematic loop in a buck regulator is the input loop, and the capacitors are placed very close to the input pins. However the return path for the capacitor to ground is indeed not optimal. A top layer ground pour should improve things. Otherwise I don't think the layout is too problematic.
This reminds me there are some telecom butterfly modules with integrated Fabry-Perot interferometers for wavelength stabilization - but I don't have experience with them. There would be two of them though, in addition to the power monitor PD. Might be niche enough that the corresponding circuitry could go on the laser adapter board.
did you check it with both opamps having min/max outputs?
It's not about capacitors being close to the input pins but the loop area
here is a paper that explains what I mean
https://www.analog.com/cn/analog-dialogue/articles/reducing-ground-bounce-in-dc-to-dc-converters.html
you can apply some solid copper and distribute the vias around pads.
are you sure? There is an option in every polygon properties. You can make all thermal relief by default and only ones requiring low thermal resistance solid. Anyway, the measurable difference occurs in GHz frequency area. In our case it doesn't matter. Impedance of 0.5mm wide, 0.25mm long trace is neglidgible. If you have 4 of them it's even lower.
Maybe add I2C/spi lines to the laser header to support them?
One can use DAC in different package like AD5680BRJZ-1500RL7
Will double check.
Interesting read. I still need some convincing and perhaps some simulations and testing to be fully on board with the idea of cutting ground planes to shape return current to reduce ground bounce. Anyways I'll reconsider the layout of the buck converter.
I was thinking more about EMI rather than ground bounce when I mentioned input capacitor placement, which is also important according to this https://www.richtek.com/Design%20Support/Technical%20Document/AN045
For most of the via under pads situations yes, but for the thermal vias under power hungry chips I think it is still better to have via under thermal pad.
Noted, thanks.
This is what we sourced to populate the V1 board.
Yes, you also need the vias to suck the tin otherwise the chip will float :)
Make sure you open the vias on the other side of the PCB to not make "acid pockets" which will shorten the PCB lifetime.
Either vias are masked on both sides or opened on both side.
I meant this by talking about ground loops https://www.analog.com/en/analog-dialogue/articles/reducing-ground-bounce-in-dc-to-dc-converters.html
if you need 3d models, you can simply unpack Altium pcbdoc file. It's container. I use 7 zip to extract all step files.
I'd add mounting holes for laser module. At least 4, with soldered Wurth standoffs. Look how I did in Thermostat EEM
I plan to make DIOT version of it sooner or later :)
there is MCU extension connector, do you plan some mezzanines in the future? I'd route 12V as well and add some mounting holes
there are grounding resistors close to the panel fixing holes. PLS add 3D model and check if they aren't too close.
The USB may not be well positioned and may not protrude through the panel
the same with power connector - it must be shifted left.
Look how thermostat_eem is done, the edge of the board is moved by ~2mm to the panel
pls make 3D model of the laser module and install on top of Kirdy to make sure there is no conflict.
you are using a lot of tantalium caps; the low ESR ones are expensive, I'd replace some of them by ceramic ones. If you need some non zero ESR, just add 0.5Ohm resistor in series.
FB8,FB9 have very low impedance in kHz region. They are good do decouple RF. I'd replace them with standard inductor; make sure you place lossy capacitor ( poor tantalium or series RC) after the inductor to not cause oscillations
add legend to:
add LEDs for critical power rails, just use 1mA current
add testpoints with labels for cricital power rails
add dual footprint for LTC6655 as we do in Stabilizer/Sampler etc, it solves issue with component availability
reference grounding is done on purpose?
if you want to keep the noise low, avoid X7R/X5R capacitors in the current source circuit due to microphonic effect.
related parts: C69, C70, C192, C13 (!), C172, C173, C152
Great :)
Yes, at least for PDH/FM spectroscopy and stabilization of diode-pumped SBS laser using a high-speed flip-flop (see end of https://193thz.com/#sbsstab2)
Thank you for your feedback. Working on a updated swiftly.
Yes. It is done on purpose for a continuous reference plane for critical analog signals.
I get how C13 may ruin the current source LD performance due to microphonic effect.
But, I saw that C69, C70 refers to the input capacitor for 9VA and 5VA. Shouldn't the output capacitors contribute more than the input capacitors instead for the microphonic effect? Then, we should also avoid X5R/X7R on the output cap as well. Similar situations for the other capacitors you mentioned.
(I attached the generated schematics here just in case)
I meant strange connections of GND in voltage reference chip
You use ceramic cap in critical place of LTM304x - at the input of the buffer. You'd better place tantalium cap there. The higher value the better.
Of course, the output capacitors also contribute, but input nosie is amplified by the LDO buffer.
The layout was drawn with reference to the sample layout in the datasheet.
Noted.