sinara-hw
/
kirdy
3
0
Fork 1
Code Issues 23 Pull Requests Projects Releases Wiki Activity
150 Commits 1 Branch 0 Tags 30 MiB
Commit Graph

150 Commits

Author SHA1 Message Date
linuswck b901f84d0a sch, pcb: Add PWR, POE_PWR netclasses 2023-11-21 11:46:46 +08:00
linuswck 20198f5eab drc: Check PWR nets clearance on pri and sec sides 
- Pri: PoE PWR nets
- Sec: PWR nets like GND, 3V3 etc
 2023-11-21 11:46:39 +08:00
linuswck 47a30da9b1 Port front panel markings design to Kicad 
- Front panel text markings can now be modified with Kicad
 2023-11-17 15:57:55 +08:00
linuswck de7c27c21f sch, pcb: Add mounting holes for Kirdy LD Adapter 2023-11-17 15:42:43 +08:00
linuswck 41db8612c0 pcb: relocate switches for better accessibility 
- modulation depth SW and termination SW are relocated
 2023-11-15 17:12:05 +08:00
linuswck de3e034c7a Add Front Panel, Kirdy LD Adapter 3D models 
- Update sch, pcb, sym lib, footrprint lib
- Position of Kirdy LD Adapter is relocated so that it is symmetric
 2023-11-15 17:11:51 +08:00
linuswck 9f3793c8fb pcb: Add 3D Models 2023-11-10 17:32:29 +08:00
linuswck 0b99a8f119 sch, pcb: Correct MFR/PN and optimize BOM 2023-11-10 15:18:22 +08:00
linuswck 7c72afe55f Remove old production files 2023-11-10 15:18:21 +08:00
linuswck cd679cf0da sch: Update Title Block Info 
- rev0.3 -> rev0_3
- Correct the title of each schematics
- Update the modified time
 2023-11-10 15:18:21 +08:00
linuswck 35da9f8c58 scripts: Add scripts to generate production files 
- The following files can be generated from the script.
1. Zipped(Gerber, Drill, Drill Map)
2. Bom,
3. Component Placement
4. Schematics PDF
5. Step Files
 2023-11-10 15:18:17 +08:00
linuswck 5ad5914748 sch, pcb: exclude MHs and soldering JP from BOM 2023-11-09 15:24:07 +08:00
linuswck a30ac45c5f pcb: Remove "designed by" silkscreen 2023-11-08 11:53:18 +08:00
linuswck 13b5f661c5 pcb: Fix TEC Polarity Connections to Header 
- Fix Issue #27
 2023-11-08 11:53:07 +08:00
linuswck 7aa84d4d23 sch: Fix incorrect TEC polarity in thermostat 
- Fix Issue #27
 2023-11-08 11:52:51 +08:00
linuswck 7b5df5150f thermostat: Fix wrong P/N in TEC Current Sense Res 
- Fix Issue #26
 2023-11-08 11:13:38 +08:00
linuswck 2a6ad78f51 pcb: Finish Layout for rev0_3 
- Assign MFR_PN for all Components
- schematics changes:
  - drivestage: Add Switch to optionally enable Modulation Signal Termination
  -             Add alternate Precision Power Resistor
  -             Modify the RC network values at TIA LPF Output
  - MCU: Add Redundant 2.54mm pitch Programming Header
  - thermostat: Duplicate the power filter network for alternate Temperature ADC
 2023-11-02 15:24:26 +08:00
linuswck 352f8c075d footprint: Add TL082Hx TI SOIC-8 footprint 2023-10-31 11:02:47 +08:00
linuswck 0c3c8a3fd1 sch: Update power related flags and nets symbols 
- Update the symbol from the kicad 7 built-in library
- Remove ERC warnings
 2023-10-31 10:29:43 +08:00
linuswck fc02f24131 sch: correct POE_VC* pins name case 
- PoE_VC* -> POE_VC*
 2023-10-31 10:23:07 +08:00
linuswck caf69e4a0f symbol: correct RJ45 VC output pin type 
- from power input to power output
 2023-10-31 10:21:18 +08:00
linuswck b0525c4d74 symbol: AD7172-4 sets DNC pin to unconnected type 2023-10-30 17:40:40 +08:00
linuswck 1f9b4e9900 sch: fix Temperature ADC SPI Connections 
- Fix Issue #25
 2023-10-30 17:32:43 +08:00
linuswck 395e104575 sch: add lpf at TEC_VSEN Buffer Output 2023-10-30 17:29:44 +08:00
linuswck 86f5addbad sch: Correct typos in TEC_~{SHDN} ports 2023-10-30 12:17:26 +08:00
linuswck f66625e431 sch: Add redundant 2.54mm SWD Header 2023-10-27 17:45:39 +08:00
linuswck fcae5b785e sch: Correct SWD Header MF/PN and Update Footprint 
- Use Adafuit 4048 Mini SWD Headers
- Silkscreen is modified to indicate orientation of the header
 2023-10-27 17:42:46 +08:00
linuswck 89dab2b553 sch: Change PoE RJ45 Jack and change PM1202 Symbol 
- Use the same PoE RJ45 as sinara-hw thermostat
- Add PM1202 Power input pins (VB+, VB-)
- Remove PoE softstart circuit as PM1202 has inrush current limiting
- Add Pi Filter at the output of PM1202
 2023-10-27 15:33:39 +08:00
linuswck 929ff58706 sch: Set DNP for DNP components 2023-10-25 17:36:20 +08:00
linuswck 57e013c9c5 sch: Support Temp ADC in alternate footprint 
- Issue #12
- Add Alternate AD7172-4BCPZ circuitry, symbol, footprint and 3D model
 2023-10-25 17:36:20 +08:00
linuswck d2c80458aa sch: Do not pass MCU RST to ETH 
- D3 -> DNP
 2023-10-25 17:36:20 +08:00
linuswck f732b9944a sch: Fix Issue #14 2023-10-25 17:36:20 +08:00
linuswck f1bda76636 sch: correct ethernet phy sigs connections to ESD 
- Pull up eth signals with 100R instead of pull down
 2023-10-25 17:36:20 +08:00
linuswck 3a1dce0107 sch: Tune LD- Out Series RC Network 
- R98 3R3 -> 10R
- C192 100n PPS -> DNP
- Add C199 2n2 in parallel C192
 2023-10-25 17:36:20 +08:00
linuswck 1fad3bf64d sch: Tune the LD V-I Output Stage Feedback Network 
- R67 -> 0R
- C175 -> 100pF
 2023-10-25 17:36:20 +08:00
linuswck e62bf3b8d6 footprint: Correct PM1202 footprint 
- enlarge courtyard and silkscreen to reflect the clearance requirement so that it can be fully seated onto the PCB
 2023-10-25 17:36:20 +08:00
linuswck dfeb1ec6a8 sch: LD DAC add parallel Cap to output resistor 
- Increase the Mod_In Signal Bandwidth
- See Issue #22
 2023-10-25 17:36:20 +08:00
linuswck 2df59fbce9 sch: Use TL082 for PD_Mon TIA and LPF Stage 2023-10-25 17:36:20 +08:00
linuswck 893f5220c6 sch: Add REF3033 for MCU ADC VREF 2023-10-25 17:36:20 +08:00
linuswck 01d0e1d45b sch: Modify dsupply freq_comp network 
- See Issue #21
 2023-10-25 17:36:20 +08:00
linuswck 566bf0317a sch: Fix Issue #15 2023-10-25 17:36:14 +08:00
linuswck 3ba3ef159e sch: Add soft start to 12V PWR Jack input 2023-10-25 17:36:14 +08:00
linuswck 5ffc2a1865 pcb: migrate to kicad 7 2023-10-25 17:35:58 +08:00
linuswck 8e5545f9c4 sch: R13 Power Resistor change to PDY10R000F 2023-10-12 12:43:03 +08:00
linuswck fcdabaee9c Mirgrate to kicad7 2023-10-12 12:26:04 +08:00
Alex Wong Tat Hang ad982265b2 improve relay power circuitry 2022-09-09 14:37:19 +08:00
Alex Wong Tat Hang 3715d93d5e clean up 2022-09-08 03:46:38 +08:00
Alex Wong Tat Hang 29cfbc9c4e finish v2 layout 2022-09-08 03:35:59 +08:00
Alex Wong Tat Hang be08d4518c some layout 2022-09-06 00:15:25 +08:00
Alex Wong Tat Hang 6aa57e04a3 update palcement 2022-09-04 23:27:58 +08:00